From bfdcfe7301da1d39cfbc4dd2ba4cc951b61a5cad Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 12 Nov 2008 23:59:01 -0600 Subject: [PATCH] bf579 --- u-boot-2008.10/MAINTAINERS | 1 + u-boot-2008.10/MAKEALL | 1 + u-boot-2008.10/Makefile | 8 +- u-boot-2008.10/blackfin_config.mk | 4 +- u-boot-2008.10/board/bf579-fpga/.gitignore | 1 + u-boot-2008.10/board/bf579-fpga/Makefile | 58 + u-boot-2008.10/board/bf579-fpga/bf579-fpga.c | 33 + u-boot-2008.10/board/bf579-fpga/config.mk | 34 + u-boot-2008.10/board/bf579-fpga/spi_flash.c | 1002 ++++++++++ u-boot-2008.10/board/bf579-fpga/u-boot.lds.S | 144 ++ u-boot-2008.10/cpu/blackfin/cpu.c | 2 +- u-boot-2008.10/cpu/blackfin/initcode.c | 171 ++- u-boot-2008.10/cpu/blackfin/traps.c | 4 + .../include/asm-blackfin/blackfin_cdef.h | 3 + u-boot-2008.10/include/asm-blackfin/blackfin_def.h | 5 + .../asm-blackfin/mach-bf579/ADSP-FRIO-core_cdef.h | 67 + .../asm-blackfin/mach-bf579/ADSP-FRIO-core_def.h | 29 + .../include/asm-blackfin/mach-bf579/BF579_cdef.h | 1947 ++++++++++++++++++++ .../include/asm-blackfin/mach-bf579/BF579_def.h | 663 +++++++ .../include/asm-blackfin/mach-bf579/anomaly.h | 140 ++ .../include/asm-blackfin/mach-bf579/def_local.h | 18 + u-boot-2008.10/include/configs/bf579-fpga.h | 118 ++ u-boot-2008.10/lib_blackfin/clocks.c | 4 +- u-boot-2008.10/lib_blackfin/string.c | 2 + 24 files changed, 4387 insertions(+), 72 deletions(-) create mode 100644 u-boot-2008.10/board/bf579-fpga/.gitignore create mode 100644 u-boot-2008.10/board/bf579-fpga/Makefile create mode 100644 u-boot-2008.10/board/bf579-fpga/bf579-fpga.c create mode 100644 u-boot-2008.10/board/bf579-fpga/config.mk create mode 100644 u-boot-2008.10/board/bf579-fpga/spi_flash.c create mode 100644 u-boot-2008.10/board/bf579-fpga/u-boot.lds.S create mode 100644 u-boot-2008.10/include/asm-blackfin/mach-bf579/ADSP-FRIO-core_cdef.h create mode 100644 u-boot-2008.10/include/asm-blackfin/mach-bf579/ADSP-FRIO-core_def.h create mode 100644 u-boot-2008.10/include/asm-blackfin/mach-bf579/BF579_cdef.h create mode 100644 u-boot-2008.10/include/asm-blackfin/mach-bf579/BF579_def.h create mode 100644 u-boot-2008.10/include/asm-blackfin/mach-bf579/anomaly.h create mode 100644 u-boot-2008.10/include/asm-blackfin/mach-bf579/def_local.h create mode 100644 u-boot-2008.10/include/configs/bf579-fpga.h diff --git a/u-boot-2008.10/MAINTAINERS b/u-boot-2008.10/MAINTAINERS index 5737fb9..92a40cc 100644 --- a/u-boot-2008.10/MAINTAINERS +++ b/u-boot-2008.10/MAINTAINERS @@ -803,6 +803,7 @@ Blackfin Team BF538F-EZKIT BF538 BF548-EZKIT BF548 BF561-EZKIT BF561 + BF579-FPGA BF579 Bluetechnix Tinyboards Blackfin Team diff --git a/u-boot-2008.10/MAKEALL b/u-boot-2008.10/MAKEALL index 234c91e..18ad14d 100755 --- a/u-boot-2008.10/MAKEALL +++ b/u-boot-2008.10/MAKEALL @@ -747,6 +747,7 @@ LIST_blackfin=" \ bf538f-ezkit \ bf548-ezkit \ bf561-ezkit \ + bf579-fpga \ blackstamp \ cm-bf527 \ cm-bf533 \ diff --git a/u-boot-2008.10/Makefile b/u-boot-2008.10/Makefile index efadb3d..bd82266 100644 --- a/u-boot-2008.10/Makefile +++ b/u-boot-2008.10/Makefile @@ -289,10 +289,7 @@ __LIBS := $(subst $(obj),,$(LIBS)) $(subst $(obj),,$(LIBBOARD)) ######################################################################### ######################################################################### -ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) $(U_BOOT_ONENAND) -ifeq ($(ARCH),blackfin) -ALL += $(obj)u-boot.ldr -endif +ALL += $(obj)u-boot.srec $(obj)System.map $(U_BOOT_NAND) $(U_BOOT_ONENAND) all: $(ALL) @@ -3045,7 +3042,7 @@ xupv2p_config: unconfig # Analog Devices boards BFIN_BOARDS = bf518f-ezbrd bf526-ezbrd bf527-ezkit bf533-ezkit bf533-stamp \ - bf537-pnav bf537-stamp bf538f-ezkit bf548-ezkit bf561-ezkit + bf537-pnav bf537-stamp bf538f-ezkit bf548-ezkit bf561-ezkit bf579-fpga # Bluetechnix tinyboards BFIN_BOARDS += cm-bf527 cm-bf533 cm-bf537e cm-bf548 cm-bf561 tcm-bf537 @@ -3217,6 +3214,7 @@ clean: $(obj)board/{integratorap,integratorcp}/u-boot.lds \ $(obj)board/{,t}cm-bf5{27,33,37e,48,61}/u-boot.lds \ $(obj)board/{bf5{18f,26,27,33,37,38f,48,61}-{ez{kit,brd},stamp}}/u-boot.lds \ + $(obj)board/bf579-fpga/u-boot.lds \ $(obj)board/{bf537-{minotaur,pnav,srv1},blackstamp}/u-boot.lds \ $(obj)cpu/blackfin/bootrom-asm-offsets.[chs] @rm -f $(obj)include/bmp_logo.h diff --git a/u-boot-2008.10/blackfin_config.mk b/u-boot-2008.10/blackfin_config.mk index 89ec3f0..c2859d8 100644 --- a/u-boot-2008.10/blackfin_config.mk +++ b/u-boot-2008.10/blackfin_config.mk @@ -34,8 +34,8 @@ ENV_IS_EMBEDDED_CUSTOM = $(call extract_define, ENV_IS_EMBEDDED_CUSTOM) PLATFORM_RELFLAGS += -ffixed-P5 -fomit-frame-pointer PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN -LDFLAGS += --gc-sections -PLATFORM_RELFLAGS += -fdata-sections +LDFLAGS += --gc-sections -O1 +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections ifneq (,$(CONFIG_BFIN_CPU)) PLATFORM_RELFLAGS += -mcpu=$(CONFIG_BFIN_CPU) diff --git a/u-boot-2008.10/board/bf579-fpga/.gitignore b/u-boot-2008.10/board/bf579-fpga/.gitignore new file mode 100644 index 0000000..945f324 --- /dev/null +++ b/u-boot-2008.10/board/bf579-fpga/.gitignore @@ -0,0 +1 @@ +/u-boot.lds diff --git a/u-boot-2008.10/board/bf579-fpga/Makefile b/u-boot-2008.10/board/bf579-fpga/Makefile new file mode 100644 index 0000000..d126593 --- /dev/null +++ b/u-boot-2008.10/board/bf579-fpga/Makefile @@ -0,0 +1,58 @@ +# +# U-boot - Makefile +# +# Copyright (c) 2005-2007 Analog Device Inc. +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o +COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +$(obj)u-boot.lds: u-boot.lds.S + $(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/u-boot-2008.10/board/bf579-fpga/bf579-fpga.c b/u-boot-2008.10/board/bf579-fpga/bf579-fpga.c new file mode 100644 index 0000000..11cb487 --- /dev/null +++ b/u-boot-2008.10/board/bf579-fpga/bf579-fpga.c @@ -0,0 +1,33 @@ +/* + * U-boot - main board file + * + * Copyright (c) 2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + printf("Board: ADI BF579-FPGA board\n"); + printf(" Support: http://blackfin.uclinux.org/\n"); + return 0; +} + +phys_size_t initdram(int board_type) +{ + gd->bd->bi_memstart = CFG_SDRAM_BASE; + gd->bd->bi_memsize = CFG_MAX_RAM_SIZE; + return CFG_MAX_RAM_SIZE; +} diff --git a/u-boot-2008.10/board/bf579-fpga/config.mk b/u-boot-2008.10/board/bf579-fpga/config.mk new file mode 100644 index 0000000..719b97e --- /dev/null +++ b/u-boot-2008.10/board/bf579-fpga/config.mk @@ -0,0 +1,34 @@ +# +# Copyright (c) 2005-2008 Analog Device Inc. +# +# (C) Copyright 2001 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# This is not actually used for Blackfin boards so do not change it +#TEXT_BASE = do-not-use-me + +LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds + +# Set some default LDR flags based on boot mode. +LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 +LDR_FLAGS-BFIN_BOOT_UART := --port g --gpio 6 +LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE)) diff --git a/u-boot-2008.10/board/bf579-fpga/spi_flash.c b/u-boot-2008.10/board/bf579-fpga/spi_flash.c new file mode 100644 index 0000000..c00c64c --- /dev/null +++ b/u-boot-2008.10/board/bf579-fpga/spi_flash.c @@ -0,0 +1,1002 @@ +/* + * SPI flash driver + * + * Enter bugs at http://blackfin.uclinux.org/ + * + * Copyright (c) 2005-2008 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +/* Configuration options: + * CONFIG_SPI_BAUD - value to load into SPI_BAUD (divisor of SCLK to get SPI CLK) + * CONFIG_SPI_FLASH_SLOW_READ - force usage of the slower read + * WARNING: make sure your SCLK + SPI_BAUD is slow enough + */ + +#include +#include +#include +#include +#include + +/* Forcibly phase out these */ +#ifdef CONFIG_SPI_FLASH_NUM_SECTORS +# error do not set CONFIG_SPI_FLASH_NUM_SECTORS +#endif +#ifdef CONFIG_SPI_FLASH_SECTOR_SIZE +# error do not set CONFIG_SPI_FLASH_SECTOR_SIZE +#endif + +#if defined(CONFIG_SPI) + +struct flash_info { + char *name; + uint16_t id; + uint16_t ext_id; + unsigned sector_size; + unsigned num_sectors; +}; + +/* SPI Speeds: 50 MHz / 33 MHz */ +static struct flash_info flash_spansion_serial_flash[] = { + { "S25FL016", 0x0215, 0, 64 * 1024, 32 }, + { "S25FL032", 0x0216, 0, 64 * 1024, 64 }, + { "S25FL064", 0x0217, 0, 64 * 1024, 128 }, + { "S25FL128-00", 0x2018, 0x0301, 64 * 1024, 256 }, /* Package marking FL128PIF */ + { "S25FL128-01", 0x2018, 0x0300, 128 * 1024, 64 }, /* Package marking FL128PIFL */ + { NULL, 0, 0, 0, 0 } +}; + +/* SPI Speeds: 50 MHz / 20 MHz */ +static struct flash_info flash_st_serial_flash[] = { + { "m25p05", 0x2010, 0, 32 * 1024, 2 }, + { "m25p10", 0x2011, 0, 32 * 1024, 4 }, + { "m25p20", 0x2012, 0, 64 * 1024, 4 }, + { "m25p40", 0x2013, 0, 64 * 1024, 8 }, + { "m25p80", 0x20FF, 0, 64 * 1024, 16 }, + { "m25p16", 0x2015, 0, 64 * 1024, 32 }, + { "m25p32", 0x2016, 0, 64 * 1024, 64 }, + { "m25p64", 0x2017, 0, 64 * 1024, 128 }, + { "m25p128", 0x2018, 0, 256 * 1024, 64 }, + { NULL, 0, 0, 0, 0 } +}; + +/* SPI Speeds: 20 MHz / 40 MHz */ +static struct flash_info flash_sst_serial_flash[] = { + { "SST25WF512", 0x2501, 0, 4 * 1024, 128 }, + { "SST25WF010", 0x2502, 0, 4 * 1024, 256 }, + { "SST25WF020", 0x2503, 0, 4 * 1024, 512 }, + { "SST25WF040", 0x2504, 0, 4 * 1024, 1024 }, + { NULL, 0, 0, 0, 0 } +}; + +/* SPI Speeds: 66 MHz / 33 MHz */ +static struct flash_info flash_atmel_dataflash[] = { + { "AT45DB011x", 0x0c, 0, 264, 512 }, + { "AT45DB021x", 0x14, 0, 264, 1025 }, + { "AT45DB041x", 0x1c, 0, 264, 2048 }, + { "AT45DB081x", 0x24, 0, 264, 4096 }, + { "AT45DB161x", 0x2c, 0, 528, 4096 }, + { "AT45DB321x", 0x34, 0, 528, 8192 }, + { "AT45DB642x", 0x3c, 0, 1056, 8192 }, + { NULL, 0, 0, 0, 0 } +}; + +/* SPI Speed: 50 MHz / 25 MHz or 40 MHz / 20 MHz */ +static struct flash_info flash_winbond_serial_flash[] = { + { "W25X10", 0x3011, 0, 16 * 256, 32 }, + { "W25X20", 0x3012, 0, 16 * 256, 64 }, + { "W25X40", 0x3013, 0, 16 * 256, 128 }, + { "W25X80", 0x3014, 0, 16 * 256, 256 }, + { "W25P80", 0x2014, 0, 256 * 256, 16 }, + { "W25P16", 0x2015, 0, 256 * 256, 32 }, + { NULL, 0, 0, 0, 0 } +}; + +struct flash_ops { + uint8_t read, write, erase, status; +}; + +#ifdef CONFIG_SPI_FLASH_SLOW_READ +# define OP_READ 0x03 +#else +# define OP_READ 0x0B +#endif +static struct flash_ops flash_st_ops = { + .read = OP_READ, + .write = 0x02, + .erase = 0xD8, + .status = 0x05, +}; + +static struct flash_ops flash_sst_ops = { + .read = OP_READ, + .write = 0x02, + .erase = 0x20, + .status = 0x05, +}; + +static struct flash_ops flash_atmel_ops = { + .read = OP_READ, + .write = 0x82, + .erase = 0x81, + .status = 0xD7, +}; + +static struct flash_ops flash_winbond_ops = { + .read = OP_READ, + .write = 0x02, + .erase = 0x20, + .status = 0x05, +}; + +struct manufacturer_info { + const char *name; + uint8_t id; + struct flash_info *flashes; + struct flash_ops *ops; +}; + +static struct { + struct manufacturer_info *manufacturer; + struct flash_info *flash; + struct flash_ops *ops; + uint8_t manufacturer_id, device_id1, device_id2, device_extid1, device_extid2; + unsigned int write_length; + unsigned long sector_size, num_sectors; +} flash; + +enum { + JED_MANU_SPANSION = 0x01, + JED_MANU_ST = 0x20, + JED_MANU_SST = 0xBF, + JED_MANU_ATMEL = 0x1F, + JED_MANU_WINBOND = 0xEF, +}; + +static struct manufacturer_info flash_manufacturers[] = { + { + .name = "Spansion", + .id = JED_MANU_SPANSION, + .flashes = flash_spansion_serial_flash, + .ops = &flash_st_ops, + }, + { + .name = "ST", + .id = JED_MANU_ST, + .flashes = flash_st_serial_flash, + .ops = &flash_st_ops, + }, + { + .name = "SST", + .id = JED_MANU_SST, + .flashes = flash_sst_serial_flash, + .ops = &flash_sst_ops, + }, + { + .name = "Atmel", + .id = JED_MANU_ATMEL, + .flashes = flash_atmel_dataflash, + .ops = &flash_atmel_ops, + }, + { + .name = "Winbond", + .id = JED_MANU_WINBOND, + .flashes = flash_winbond_serial_flash, + .ops = &flash_winbond_ops, + }, +}; + +#define TIMEOUT 5000 /* timeout of 5 seconds */ + +/* If part has multiple SPI flashes, assume SPI0 as that is + * the one we can boot off of ... + */ +#ifndef pSPI_CTL +# define pSPI_CTL pSPI0_CTL +# define pSPI_BAUD pSPI0_BAUD +# define pSPI_FLG pSPI0_FLG +# define pSPI_RDBR pSPI0_RDBR +# define pSPI_STAT pSPI0_STAT +# define pSPI_TDBR pSPI0_TDBR +#endif + +/* Default to the SPI SSEL that we boot off of: + * BF54x, BF537, (everything new?): SSEL1 + * BF51x, BF533, BF561: SSEL2 + */ +#ifndef CONFIG_SPI_FLASH_SSEL +# if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \ + defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) || \ + defined(__ADSPBF51x__) +# define CONFIG_SPI_FLASH_SSEL 2 +# else +# define CONFIG_SPI_FLASH_SSEL 1 +# endif +#endif +#define SSEL_MASK (1 << CONFIG_SPI_FLASH_SSEL) + +static void SPI_INIT(void) +{ + /* [#3541] This delay appears to be necessary, but not sure + * exactly why as the history behind it is non-existant. + */ + *pSPI_CTL = 0; + udelay(CONFIG_CCLK_HZ / 25000000); + + /* enable SPI pins: SSEL, MOSI, MISO, SCK */ +#ifdef __ADSPBF54x__ + *pPORTE_FER |= (PE0 | PE1 | PE2 | PE4); +#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__) + *pPORTF_FER |= (PF10 | PF11 | PF12 | PF13); +#elif defined(__ADSPBF52x__) + bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_3); + bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG1 | PG2 | PG3 | PG4); +#elif defined(__ADSPBF51x__) + bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_7_MASK) | PORT_x_MUX_7_FUNC_1); + bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG12 | PG13 | PG14 | PG15); +#endif + + /* initate communication upon write of TDBR */ + *pSPI_CTL = (SPE | MSTR | CPHA | CPOL | TDBR_CORE); + *pSPI_BAUD = CONFIG_SPI_BAUD; +} + +static void SPI_DEINIT(void) +{ + *pSPI_CTL = 0; + *pSPI_BAUD = 0; + SSYNC(); +} + +static void SPI_ON(void) +{ + /* toggle SSEL to reset the device so it'll take a new command */ + *pSPI_FLG = 0xFF00 | SSEL_MASK; + SSYNC(); + + *pSPI_FLG = ((0xFF & ~SSEL_MASK) << 8) | SSEL_MASK; + SSYNC(); +} + +static void SPI_OFF(void) +{ + /* put SPI settings back to reset state */ + *pSPI_FLG = 0xFF00; + SSYNC(); +} + +static uint8_t spi_write_read_byte(uint8_t transmit) +{ + *pSPI_TDBR = transmit; + SSYNC(); + + while ((*pSPI_STAT & TXS)) + if (ctrlc()) + break; + while (!(*pSPI_STAT & SPIF)) + if (ctrlc()) + break; + while (!(*pSPI_STAT & RXS)) + if (ctrlc()) + break; + + /* Read dummy to empty the receive register */ + return *pSPI_RDBR; +} + +static uint8_t read_status_register(void) +{ + uint8_t status_register; + + /* send instruction to read status register */ + SPI_ON(); + spi_write_read_byte(flash.ops->status); + /* send dummy to receive the status register */ + status_register = spi_write_read_byte(0); + SPI_OFF(); + + return status_register; +} + +static int wait_for_ready_status(void) +{ + ulong start = get_timer(0); + + while (get_timer(0) - start < TIMEOUT) { + switch (flash.manufacturer_id) { + case JED_MANU_SPANSION: + case JED_MANU_ST: + case JED_MANU_SST: + case JED_MANU_WINBOND: + if (!(read_status_register() & 0x01)) + return 0; + break; + + case JED_MANU_ATMEL: + if (read_status_register() & 0x80) + return 0; + break; + } + + if (ctrlc()) { + puts("\nAbort\n"); + return -1; + } + } + + puts("Timeout\n"); + return -1; +} + +static int enable_writing(void) +{ + ulong start; + + if (flash.manufacturer_id == JED_MANU_ATMEL) + return 0; + + /* A write enable instruction must previously have been executed */ + SPI_ON(); + spi_write_read_byte(0x06); + SPI_OFF(); + + /* The status register will be polled to check the write enable latch "WREN" */ + start = get_timer(0); + while (get_timer(0) - start < TIMEOUT) { + if (read_status_register() & 0x02) + return 0; + + if (ctrlc()) { + puts("\nAbort\n"); + return -1; + } + } + + puts("Timeout\n"); + return -1; +} + +static void write_status_register(uint8_t val) +{ + if (flash.manufacturer_id != JED_MANU_SST) + hang(); + + if (enable_writing()) + return; + + /* send instruction to write status register */ + SPI_ON(); + spi_write_read_byte(0x01); + /* and clear it! */ + spi_write_read_byte(val); + SPI_OFF(); +} + +/* Request and read the manufacturer and device id of parts which + * are compatible with the JEDEC standard (JEP106) and use that to + * setup other operating conditions. + */ +static int spi_detect_part(void) +{ + uint16_t dev_id, dev_extid; + size_t i; + + static char called_init; + if (called_init) + return 0; + +#ifdef CONFIG_SPI_FLASH_M25P80 + flash.manufacturer_id = JED_MANU_ST; + flash.device_id1 = 0x20; + flash.device_id2 = 0xFF; +#else + SPI_ON(); + + /* Send the request for the part identification */ + spi_write_read_byte(0x9F); + + /* Now read in the manufacturer id bytes */ + do { + flash.manufacturer_id = spi_write_read_byte(0); + if (flash.manufacturer_id == 0x7F) + puts("Warning: unhandled manufacturer continuation byte!\n"); + } while (flash.manufacturer_id == 0x7F); + + /* Now read in the first device id byte */ + flash.device_id1 = spi_write_read_byte(0); + + /* Now read in the second device id byte */ + flash.device_id2 = spi_write_read_byte(0); + + /* Read extended device ids */ + flash.device_extid1 = spi_write_read_byte(0); + flash.device_extid2 = spi_write_read_byte(0); + + SPI_OFF(); +#endif + + dev_id = (flash.device_id1 << 8) | flash.device_id2; + dev_extid = (flash.device_extid1 << 8) | flash.device_extid2; + + for (i = 0; i < ARRAY_SIZE(flash_manufacturers); ++i) { + if (flash.manufacturer_id == flash_manufacturers[i].id) + break; + } + if (i == ARRAY_SIZE(flash_manufacturers)) + goto unknown; + + flash.manufacturer = &flash_manufacturers[i]; + flash.ops = flash_manufacturers[i].ops; + + switch (flash.manufacturer_id) { + case JED_MANU_SPANSION: + case JED_MANU_ST: + case JED_MANU_SST: + case JED_MANU_WINBOND: + for (i = 0; flash.manufacturer->flashes[i].name; ++i) { + if (dev_id == flash.manufacturer->flashes[i].id && + (flash.manufacturer->flashes[i].ext_id == 0 || + flash.manufacturer->flashes[i].ext_id == dev_extid)) + break; + } + if (!flash.manufacturer->flashes[i].name) + goto unknown; + + flash.flash = &flash.manufacturer->flashes[i]; + flash.sector_size = flash.flash->sector_size; + flash.num_sectors = flash.flash->num_sectors; + + if (flash.manufacturer_id == JED_MANU_SST) + flash.write_length = 1; /* pwnt :( */ + else + flash.write_length = 256; + break; + + case JED_MANU_ATMEL: { + uint8_t status = read_status_register(); + + for (i = 0; flash.manufacturer->flashes[i].name; ++i) { + if ((status & 0x3c) == flash.manufacturer->flashes[i].id) + break; + } + if (!flash.manufacturer->flashes[i].name) + goto unknown; + + flash.flash = &flash.manufacturer->flashes[i]; + flash.sector_size = flash.flash->sector_size; + flash.num_sectors = flash.flash->num_sectors; + + /* see if flash is in "power of 2" mode */ + if (status & 0x1) + flash.sector_size &= ~(1 << (ffs(flash.sector_size) - 1)); + + flash.write_length = flash.sector_size; + break; + } + } + + /* the SST parts power up with software protection enabled by default */ + if (flash.manufacturer_id == JED_MANU_SST) + write_status_register(0); + + called_init = 1; + return 0; + + unknown: + printf("Unknown SPI device: 0x%02X 0x%02X 0x%02X\n", + flash.manufacturer_id, flash.device_id1, flash.device_id2); + return 1; +} + +/* + * Function: spi_init_f + * Description: Init SPI-Controller (ROM part) + * return: --- + */ +void spi_init_f(void) +{ +} + +/* + * Function: spi_init_r + * Description: Init SPI-Controller (RAM part) - + * The malloc engine is ready and we can move our buffers to + * normal RAM + * return: --- + */ +void spi_init_r(void) +{ +#if defined(CONFIG_POST) && (CONFIG_POST & CFG_POST_SPI) + /* Our testing strategy here is pretty basic: + * - fill src memory with an 8-bit pattern + * - write the src memory to the SPI flash + * - read the SPI flash into the dst memory + * - compare src and dst memory regions + * - repeat a few times + * The variations we test for: + * - change the 8-bit pattern a bit + * - change the read/write block size so we know: + * - writes smaller/equal/larger than the buffer work + * - writes smaller/equal/larger than the sector work + * - change the SPI offsets so we know: + * - writing partial sectors works + */ + uint8_t *mem_src, *mem_dst; + size_t i, c, l, o; + size_t test_count, errors; + uint8_t pattern; + + SPI_INIT(); + + if (spi_detect_part()) + goto out; + eeprom_info(); + + ulong lengths[] = { + flash.write_length, + flash.write_length * 2, + flash.write_length / 2, + flash.sector_size, + flash.sector_size * 2, + flash.sector_size / 2 + }; + ulong offsets[] = { + 0, + flash.write_length, + flash.write_length * 2, + flash.write_length / 2, + flash.write_length / 4, + flash.sector_size, + flash.sector_size * 2, + flash.sector_size / 2, + flash.sector_size / 4, + }; + + /* the exact addresses are arbitrary ... they just need to not overlap */ + mem_src = (void *)(0); + mem_dst = (void *)(max(flash.write_length, flash.sector_size) * 2); + + test_count = 0; + errors = 0; + pattern = 0x00; + + for (i = 0; i < 16; ++i) { /* 16 = 8 bits * 2 iterations */ + for (l = 0; l < ARRAY_SIZE(lengths); ++l) { + for (o = 0; o < ARRAY_SIZE(offsets); ++o) { + ulong len = lengths[l]; + ulong off = offsets[o]; + + printf("Testing pattern 0x%02X of length %5lu and offset %5lu: ", pattern, len, off); + + /* setup the source memory region */ + memset(mem_src, pattern, len); + + test_count += 4; + for (c = 0; c < 4; ++c) { /* 4 is just a random repeat count */ + if (ctrlc()) { + puts("\nAbort\n"); + goto out; + } + + /* make sure background fill pattern != pattern */ + memset(mem_dst, pattern ^ 0xFF, len); + + /* write out the source memory and then read it back and compare */ + eeprom_write(0, off, mem_src, len); + eeprom_read(0, off, mem_dst, len); + + if (memcmp(mem_src, mem_dst, len)) { + for (c = 0; c < len; ++c) + if (mem_src[c] != mem_dst[c]) + break; + printf(" FAIL @ offset %u, skipping repeats ", c); + ++errors; + break; + } + + /* XXX: should shrink write region here to test with + * leading/trailing canaries so we know surrounding + * bytes don't get screwed. + */ + } + puts("\n"); + } + } + + /* invert the pattern every other run and shift out bits slowly */ + pattern ^= 0xFF; + if (i % 2) + pattern = (pattern | 0x01) << 1; + } + + if (errors) + printf("SPI FAIL: Out of %i tests, there were %i errors ;(\n", test_count, errors); + else + printf("SPI PASS: %i tests worked!\n", test_count); + + out: + SPI_DEINIT(); + +#endif +} + +static void transmit_address(uint32_t addr) +{ + /* Send the highest byte of the 24 bit address at first */ + spi_write_read_byte(addr >> 16); + /* Send the middle byte of the 24 bit address at second */ + spi_write_read_byte(addr >> 8); + /* Send the lowest byte of the 24 bit address finally */ + spi_write_read_byte(addr); +} + +/* + * Read a value from flash for verify purpose + * Inputs: unsigned long ulStart - holds the SPI start address + * int pnData - pointer to store value read from flash + * long lCount - number of elements to read + */ +#ifdef CONFIG_SPI_READFLASH_NODMA +static int read_flash(unsigned long address, long count, uchar *buffer) +{ + size_t i, j; + + /* Send the read command to SPI device */ + SPI_ON(); + spi_write_read_byte(flash.ops->read); + transmit_address(address); + +#ifndef CONFIG_SPI_FLASH_SLOW_READ + /* Send dummy byte when doing SPI fast reads */ + spi_write_read_byte(0); +#endif + + /* After the SPI device address has been placed on the MOSI pin the data can be */ + /* received on the MISO pin. */ + j = flash.sector_size << 1; + for (i = 1; i <= count; ++i) { + *buffer++ = spi_write_read_byte(0); + if (!j--) { + puts("."); + j = flash.sector_size; + } + } + + SPI_OFF(); + + return 0; +} +#else + +#ifdef __ADSPBF54x__ +#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA4_IRQ_STATUS +#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA4_IRQ_STATUS +#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA4_CURR_DESC_PTR +#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA4_CONFIG +#elif defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__) || \ + defined(__ADSPBF538__) || defined(__ADSPBF539__) +#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA5_IRQ_STATUS +#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA5_IRQ_STATUS +#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA5_CURR_DESC_PTR +#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA5_CONFIG +#elif defined(__ADSPBF561__) +#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA16_IRQ_STATUS +#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA16_IRQ_STATUS +#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA16_CURR_DESC_PTR +#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA16_CONFIG +#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) || \ + defined(__ADSPBF52x__) || defined(__ADSPBF51x__) +#define bfin_write_DMA_SPI_IRQ_STATUS bfin_write_DMA7_IRQ_STATUS +#define bfin_read_DMA_SPI_IRQ_STATUS bfin_read_DMA7_IRQ_STATUS +#define bfin_write_DMA_SPI_CURR_DESC_PTR bfin_write_DMA7_CURR_DESC_PTR +#define bfin_write_DMA_SPI_CONFIG bfin_write_DMA7_CONFIG +#else +#error "Please provide SPI DMA channel defines" +#endif + +struct dmadesc_array { + unsigned long start_addr; + unsigned short cfg; + unsigned short x_count; + short x_modify; + unsigned short y_count; + short y_modify; +} __attribute__((packed)); + +/* + * Read a value from flash for verify purpose + * Inputs: unsigned long ulStart - holds the SPI start address + * int pnData - pointer to store value read from flash + * long lCount - number of elements to read + */ + +static int read_flash(unsigned long address, long count, uchar *buffer) +{ + unsigned int ndsize; + struct dmadesc_array dma[2]; + /* Send the read command to SPI device */ + + if (!count) + return 0; + + dma[0].start_addr = (unsigned long)buffer; + dma[0].x_modify = 1; + if (count <= 65536) { + blackfin_dcache_flush_invalidate_range(buffer, buffer + count); + ndsize = NDSIZE_5; + dma[0].cfg = NDSIZE_0 | WNR | WDSIZE_8 | FLOW_STOP | DMAEN | DI_EN; + dma[0].x_count = count; + } else { + blackfin_dcache_flush_invalidate_range(buffer, buffer + 65536 - 1); + ndsize = NDSIZE_7; + dma[0].cfg = NDSIZE_5 | WNR | WDSIZE_8 | FLOW_ARRAY | DMAEN | DMA2D; + dma[0].x_count = 0; /* 2^16 */ + dma[0].y_count = count >> 16; /* count / 2^16 */ + dma[0].y_modify = 1; + dma[1].start_addr = (unsigned long)(buffer + (count & ~0xFFFF)); + dma[1].cfg = NDSIZE_0 | WNR | WDSIZE_8 | FLOW_STOP | DMAEN | DI_EN; + dma[1].x_count = count & 0xFFFF; /* count % 2^16 */ + dma[1].x_modify = 1; + } + + bfin_write_DMA_SPI_CONFIG(0); + bfin_write_DMA_SPI_IRQ_STATUS(DMA_DONE | DMA_ERR); + bfin_write_DMA_SPI_CURR_DESC_PTR(dma); + + SPI_ON(); + + spi_write_read_byte(flash.ops->read); + transmit_address(address); + +#ifndef CONFIG_SPI_FLASH_SLOW_READ + /* Send dummy byte when doing SPI fast reads */ + spi_write_read_byte(0); +#endif + + bfin_write_DMA_SPI_CONFIG(ndsize | FLOW_ARRAY | DMAEN); + *pSPI_CTL = (MSTR | CPHA | CPOL | RDBR_DMA | SPE | SZ); + SSYNC(); + + /* + * We already invalidated the first 64k, + * now while we just wait invalidate the remaining part. + * Its not likely that the DMA is going to overtake + */ + if (count > 65536) + blackfin_dcache_flush_invalidate_range(buffer + 65536, + buffer + count); + + while (!(bfin_read_DMA_SPI_IRQ_STATUS() & DMA_DONE)) + if (ctrlc()) + break; + + SPI_OFF(); + + *pSPI_CTL = 0; + + bfin_write_DMA_SPI_CONFIG(0); + + *pSPI_CTL = (SPE | MSTR | CPHA | CPOL | TDBR_CORE); + + return 0; +} +#endif + +static long address_to_sector(unsigned long address) +{ + if (address > (flash.num_sectors * flash.sector_size) - 1) + return -1; + return address / flash.sector_size; +} + +static int erase_sector(int address) +{ + /* sector gets checked in higher function, so assume it's valid + * here and figure out the offset of the sector in flash + */ + if (enable_writing()) + return -1; + + /* + * Send the erase block command to the flash followed by the 24 address + * to point to the start of a sector + */ + SPI_ON(); + spi_write_read_byte(flash.ops->erase); + transmit_address(address); + SPI_OFF(); + + return wait_for_ready_status(); +} + +/* Write [count] bytes out of [buffer] into the given SPI [address] */ +static long write_flash(unsigned long address, long count, uchar *buffer) +{ + long i, write_buffer_size; + + if (enable_writing()) + return -1; + + /* Send write command followed by the 24 bit address */ + SPI_ON(); + spi_write_read_byte(flash.ops->write); + transmit_address(address); + + /* Shoot out a single write buffer */ + write_buffer_size = min(count, flash.write_length); + for (i = 0; i < write_buffer_size; ++i) + spi_write_read_byte(buffer[i]); + + SPI_OFF(); + + /* Wait for the flash to do its thing */ + if (wait_for_ready_status()) { + puts("SPI Program Time out! "); + return -1; + } + + return i; +} + +/* Write [count] bytes out of [buffer] into the given SPI [address] */ +static int write_sector(unsigned long address, long count, uchar *buffer) +{ + long write_cnt; + + while (count != 0) { + write_cnt = write_flash(address, count, buffer); + if (write_cnt == -1) + return -1; + + /* Now that we've sent some bytes out to the flash, update + * our counters a bit + */ + count -= write_cnt; + address += write_cnt; + buffer += write_cnt; + } + + /* return the appropriate error code */ + return 0; +} + +/* + * Function: spi_write + */ +ssize_t spi_write(uchar *addr, int alen, uchar *buffer, int len) +{ + unsigned long offset; + int start_sector, end_sector; + int start_byte, end_byte; + uchar *temp = NULL; + int num, ret = 0; + + SPI_INIT(); + + if (spi_detect_part()) + goto out; + + offset = addr[0] << 16 | addr[1] << 8 | addr[2]; + + /* Get the start block number */ + start_sector = address_to_sector(offset); + if (start_sector == -1) { + puts("Invalid sector! "); + goto out; + } + end_sector = address_to_sector(offset + len - 1); + if (end_sector == -1) { + puts("Invalid sector! "); + goto out; + } + + /* Since flashes operate in sector units but the eeprom command + * operates as a continuous stream of bytes, we need to emulate + * the eeprom behavior. So here we read in the sector, overlay + * any bytes we're actually modifying, erase the sector, and + * then write back out the new sector. + */ + temp = malloc(flash.sector_size); + if (!temp) { + puts("Malloc for sector failed! "); + goto out; + } + + for (num = start_sector; num <= end_sector; num++) { + unsigned long address = num * flash.sector_size; + + /* XXX: should add an optimization when spanning sectors: + * No point in reading in a sector if we're going to be + * clobbering the whole thing. Need to also add a test + * case to make sure the optimization is correct. + */ + if (read_flash(address, flash.sector_size, temp)) { + puts("Read sector failed! "); + len = 0; + break; + } + + start_byte = max(address, offset); + end_byte = address + flash.sector_size - 1; + if (end_byte > (offset + len)) + end_byte = (offset + len - 1); + + memcpy(temp + start_byte - address, + buffer + start_byte - offset, + end_byte - start_byte + 1); + + if (erase_sector(address)) { + puts("Erase sector failed! "); + goto out; + } + + if (write_sector(address, flash.sector_size, temp)) { + puts("Write sector failed! "); + goto out; + } + + puts("."); + } + + ret = len; + + out: + free(temp); + + SPI_DEINIT(); + + return ret; +} + +/* + * Function: spi_read + */ +ssize_t spi_read(uchar *addr, int alen, uchar *buffer, int len) +{ + unsigned long offset; + + SPI_INIT(); + + if (spi_detect_part()) + len = 0; + else { + offset = addr[0] << 16 | addr[1] << 8 | addr[2]; + read_flash(offset, len, buffer); + } + + SPI_DEINIT(); + + return len; +} + +/* + * Spit out some useful information about the SPI eeprom + */ +int eeprom_info(void) +{ + int ret = 0; + + SPI_INIT(); + + if (spi_detect_part()) + ret = 1; + else + printf("SPI Device: %s 0x%02X (%s) 0x%02X 0x%02X\n" + "Parameters: num sectors = %lu, sector size = %lu, write size = %i\n" + "Flash Size: %lu mbit (%lu mbyte)\n" + "Status: 0x%02X\n", + flash.flash->name, flash.manufacturer_id, flash.manufacturer->name, + flash.device_id1, flash.device_id2, flash.num_sectors, + flash.sector_size, flash.write_length, + (flash.num_sectors * flash.sector_size) >> 17, + (flash.num_sectors * flash.sector_size) >> 20, + read_status_register()); + + SPI_DEINIT(); + + return ret; +} + +#endif diff --git a/u-boot-2008.10/board/bf579-fpga/u-boot.lds.S b/u-boot-2008.10/board/bf579-fpga/u-boot.lds.S new file mode 100644 index 0000000..e836b0e --- /dev/null +++ b/u-boot-2008.10/board/bf579-fpga/u-boot.lds.S @@ -0,0 +1,144 @@ +/* + * U-boot - u-boot.lds.S + * + * Copyright (c) 2005-2008 Analog Device Inc. + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#undef ALIGN +#undef ENTRY +#undef bfin + +/* If we don't actually load anything into L1 data, this will avoid + * a syntax error. If we do actually load something into L1 data, + * we'll get a linker memory load error (which is what we'd want). + * This is here in the first place so we can quickly test building + * for different CPU's which may lack non-cache L1 data. + */ +#ifndef L1_DATA_B_SRAM +# define L1_DATA_B_SRAM CFG_MONITOR_BASE +# define L1_DATA_B_SRAM_SIZE 0 +#endif + +OUTPUT_ARCH(bfin) + +MEMORY +{ +// ram : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN + l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE + l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE + l1_bss : ORIGIN = L1_DATA_A_SRAM, LENGTH = L1_DATA_A_SRAM_SIZE +} + +ENTRY(_start) +SECTIONS +{ + .text : + { + cpu/blackfin/start.o (.text .text.*) + +#ifdef ENV_IS_EMBEDDED + /* WARNING - the following is hand-optimized to fit within + * the sector before the environment sector. If it throws + * an error during compilation remove an object here to get + * it linked after the configuration sector. + */ + + cpu/blackfin/traps.o (.text .text.*) + cpu/blackfin/interrupt.o (.text .text.*) + cpu/blackfin/serial.o (.text .text.*) + common/dlmalloc.o (.text .text.*) + lib_generic/crc32.o (.text .text.*) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o (.text .text.*) +#endif + + __initcode_start = .; + cpu/blackfin/initcode.o (.text .text.*) + __initcode_end = .; + + *(.text .text.*) + } >l1_code + + .rodata : + { + . = ALIGN(4); + *(.rodata .rodata.*) + *(.rodata1) + *(.eh_frame) + . = ALIGN(4); + } >l1_data + + .data : + { + . = ALIGN(256); + *(.data .data.*) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } >l1_data + + .u_boot_cmd : + { + ___u_boot_cmd_start = .; + *(.u_boot_cmd) + ___u_boot_cmd_end = .; + } >l1_data + + .text_l1 : + { + . = ALIGN(4); + __stext_l1 = .; + *(.l1.text) + . = ALIGN(4); + __etext_l1 = .; + } >l1_code + __stext_l1_lma = LOADADDR(.text_l1); + + .data_l1 : + { + . = ALIGN(4); + __sdata_l1 = .; + *(.l1.data) + *(.l1.bss) + . = ALIGN(4); + __edata_l1 = .; + } >l1_data + __sdata_l1_lma = LOADADDR(.data_l1); + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss .bss.*) + *(COMMON) + __bss_end = .; + } >l1_bss +} diff --git a/u-boot-2008.10/cpu/blackfin/cpu.c b/u-boot-2008.10/cpu/blackfin/cpu.c index c2ff8cd..f83cc8e 100644 --- a/u-boot-2008.10/cpu/blackfin/cpu.c +++ b/u-boot-2008.10/cpu/blackfin/cpu.c @@ -81,7 +81,7 @@ int irq_init(void) #elif defined(SICA_IMASK0) bfin_write_SICA_IMASK0(0); bfin_write_SICA_IMASK1(0); -#else +#elif defined(SIC_IMASK) bfin_write_SIC_IMASK(0); #endif bfin_write_EVT2(evt_default); /* NMI */ diff --git a/u-boot-2008.10/cpu/blackfin/initcode.c b/u-boot-2008.10/cpu/blackfin/initcode.c index a08e626..3b83ef2 100644 --- a/u-boot-2008.10/cpu/blackfin/initcode.c +++ b/u-boot-2008.10/cpu/blackfin/initcode.c @@ -269,13 +269,9 @@ static inline void serial_putc(char c) #endif #endif -BOOTROM_CALLED_FUNC_ATTR -void initcode(ADI_BOOT_DATA *bootstruct) +__attribute__((always_inline)) +static inline void program_early_devices(ADI_BOOT_DATA *bootstruct) { - uint32_t old_baud = serial_init(); - - serial_putc('A'); - #ifdef CONFIG_HW_WATCHDOG # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE # define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000 @@ -287,53 +283,33 @@ void initcode(ADI_BOOT_DATA *bootstruct) * timeout, so don't clobber that. */ if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) { + serial_putc('a'); bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE)); bfin_write_WDOG_CTL(0); } #endif - serial_putc('B'); - - /* If external memory is enabled, put it into self refresh first. */ - bool put_into_srfs = false; -#ifdef EBIU_RSTCTL - if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) { - bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ); - put_into_srfs = true; - } -#else - if (bfin_read_EBIU_SDBCTL() & EBE) { - bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS); - put_into_srfs = true; - } -#endif - - serial_putc('C'); - /* Blackfin bootroms use the SPI slow read opcode instead of the SPI * fast read, so we need to slow down the SPI clock a lot more during * boot. Once we switch over to u-boot's SPI flash driver, we'll * increase the speed appropriately. */ - if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) + if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) { + serial_putc('b'); #ifdef SPI0_BAUD bfin_write_SPI0_BAUD(CONFIG_SPI_BAUD_INITBLOCK); #else bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK); #endif + } +} - serial_putc('D'); - - /* If we're entering self refresh, make sure it has happened. */ - if (put_into_srfs) -#ifdef EBIU_RSTCTL - while (!(bfin_read_EBIU_RSTCTL() & SRACK)) -#else - while (!(bfin_read_EBIU_SDSTAT() & SDSRA)) +__attribute__((always_inline)) +static inline uint16_t program_clocks(ADI_BOOT_DATA *bootstruct) +{ +#ifdef CONFIG_BFIN_NO_INIT_CLOCKS + return 0; #endif - continue; - - serial_putc('E'); /* With newer bootroms, we use the helper function to set up * the memory controller. Older bootroms lacks such helpers @@ -341,7 +317,7 @@ void initcode(ADI_BOOT_DATA *bootstruct) */ uint16_t vr_ctl = bfin_read_VR_CTL(); if (!ANOMALY_05000386) { - serial_putc('F'); + serial_putc('a'); ADI_SYSCTRL_VALUES memory_settings; uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV | SYSCTRL_LOCKCNT; @@ -359,7 +335,7 @@ void initcode(ADI_BOOT_DATA *bootstruct) memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL; bfrom_SysControl(actions, &memory_settings, NULL); } else { - serial_putc('G'); + serial_putc('b'); /* Disable all peripheral wakeups except for the PLL event. */ #ifdef SIC_IWR0 @@ -375,39 +351,34 @@ void initcode(ADI_BOOT_DATA *bootstruct) bfin_write_SIC_IWR(1); #endif - serial_putc('H'); - + serial_putc('c'); bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL); - serial_putc('I'); - /* Only reprogram when needed to avoid triggering unnecessary * PLL relock sequences. */ + serial_putc('d'); if (vr_ctl != CONFIG_VR_CTL_VAL) { serial_putc('!'); bfin_write_VR_CTL(CONFIG_VR_CTL_VAL); asm("idle;"); } - serial_putc('J'); - + serial_putc('e'); bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL); - serial_putc('K'); - /* Only reprogram when needed to avoid triggering unnecessary * PLL relock sequences. */ + serial_putc('f'); if (bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) { serial_putc('!'); bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL); asm("idle;"); } - serial_putc('L'); - /* Restore all peripheral wakeups. */ + serial_putc('g'); #ifdef SIC_IWR0 bfin_write_SIC_IWR0(-1); bfin_write_SIC_IWR1(-1); @@ -422,27 +393,63 @@ void initcode(ADI_BOOT_DATA *bootstruct) #endif } - serial_putc('M'); + return vr_ctl; +} - /* Since we've changed the SCLK above, we may need to update - * the UART divisors (UART baud rates are based on SCLK). +__attribute__((always_inline)) +static inline bool maybe_self_refresh(ADI_BOOT_DATA *bootstruct) +{ + bool put_into_srfs = false; + +#ifdef CONFIG_BFIN_NO_EXTERNAL_MEMORY + return put_into_srfs; +#endif + + /* If external memory is enabled, put it into self refresh first. + * This way we can safely reprogram clocks and memory settings. */ - serial_reset_baud(old_baud); + serial_putc('a'); - serial_putc('N'); +#ifdef EBIU_RSTCTL + if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) { + serial_putc('b'); + bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ); + put_into_srfs = true; + + serial_putc('c'); + while (!(bfin_read_EBIU_RSTCTL() & SRACK)) + continue; + } +#else + if (bfin_read_EBIU_SDBCTL() & EBE) { + serial_putc('d'); + bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS); + put_into_srfs = true; + + serial_putc('e'); + while (!(bfin_read_EBIU_SDSTAT() & SDSRA)) + continue; + } +#endif + return put_into_srfs; +} + +__attribute__((always_inline)) +static inline void program_memory_controller(ADI_BOOT_DATA *bootstruct, bool put_into_srfs) +{ /* Program the external memory controller before we come out of * self-refresh. This only works with our SDRAM controller. */ #ifndef EBIU_RSTCTL + serial_putc('a'); bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL); bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL); bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL); #endif - serial_putc('O'); - /* Now that we've reprogrammed, take things out of self refresh. */ + serial_putc('b'); if (put_into_srfs) #ifdef EBIU_RSTCTL bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ)); @@ -450,12 +457,11 @@ void initcode(ADI_BOOT_DATA *bootstruct) bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS)); #endif - serial_putc('P'); - /* Our DDR controller sucks and cannot be programmed while in * self-refresh. So we have to pull it out before programming. */ #ifdef EBIU_RSTCTL + serial_putc('c'); bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL); bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL); bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL); @@ -468,8 +474,14 @@ void initcode(ADI_BOOT_DATA *bootstruct) bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | CONFIG_EBIU_DDRQUE_VAL); # endif #endif +} - serial_putc('Q'); +__attribute__((always_inline)) +static inline void check_hibernation(uint16_t vr_ctl) +{ +#ifdef CONFIG_BFIN_NO_EXTERNAL_MEMORY + return; +#endif /* Are we coming out of hibernate (suspend to memory) ? * The memory layout is: @@ -479,11 +491,12 @@ void initcode(ADI_BOOT_DATA *bootstruct) * * SCKELOW is unreliable on older parts (anomaly 307) */ + serial_putc('a'); if (ANOMALY_05000307 || vr_ctl & 0x8000) { uint32_t *hibernate_magic = 0; __builtin_bfin_ssync(); /* make sure memory controller is done */ if (hibernate_magic[0] == 0xDEADBEEF) { - serial_putc('R'); + serial_putc('b'); bfin_write_EVT15(hibernate_magic[1]); bfin_write_IMASK(EVT_IVG15); __asm__ __volatile__ ( @@ -501,24 +514,58 @@ void initcode(ADI_BOOT_DATA *bootstruct) ); } } +} - serial_putc('S'); - +__attribute__((always_inline)) +static inline void program_ebiu(ADI_BOOT_DATA *bootstruct) +{ + serial_putc('a'); /* Program the async banks controller. */ bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL); bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL); bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL); #ifdef EBIU_MODE + serial_putc('b'); /* Not all parts have these additional MMRs. */ bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL); bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL); bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL); #endif +} + +BOOTROM_CALLED_FUNC_ATTR +void initcode(ADI_BOOT_DATA *bootstruct) +{ + uint32_t old_baud = serial_init(); + uint16_t vr_ctl; + bool put_into_srfs; + + serial_putc('A'); + program_early_devices(bootstruct); + + serial_putc('B'); + put_into_srfs = maybe_self_refresh(bootstruct); + + serial_putc('C'); + vr_ctl = program_clocks(bootstruct); + + /* Since we've changed the SCLK above, we may need to update + * the UART divisors (UART baud rates are based on SCLK). + */ + serial_reset_baud(old_baud); + + serial_putc('D'); + program_memory_controller(bootstruct, put_into_srfs); + + serial_putc('E'); + check_hibernation(vr_ctl); - serial_putc('T'); + serial_putc('F'); + program_ebiu(bootstruct); /* tell the bootrom where our entry point is */ + serial_putc('G'); if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) bfin_write_EVT1(CFG_MONITOR_BASE); diff --git a/u-boot-2008.10/cpu/blackfin/traps.c b/u-boot-2008.10/cpu/blackfin/traps.c index af3d990..188e37c 100644 --- a/u-boot-2008.10/cpu/blackfin/traps.c +++ b/u-boot-2008.10/cpu/blackfin/traps.c @@ -227,10 +227,12 @@ static void decode_address(char *buf, unsigned long address) static char *strhwerrcause(uint16_t hwerrcause) { switch (hwerrcause) { +#ifdef CONFIG_DEBUG_VERBOSE_FAULT case 0x02: return "system mmr error"; case 0x03: return "external memory addressing error"; case 0x12: return "performance monitor overflow"; case 0x18: return "raise 5 instruction"; +#endif default: return "undef"; } } @@ -238,6 +240,7 @@ static char *strhwerrcause(uint16_t hwerrcause) static char *strexcause(uint16_t excause) { switch (excause) { +#ifdef CONFIG_DEBUG_VERBOSE_FAULT case 0x00 ... 0xf: return "custom exception"; case 0x10: return "single step"; case 0x11: return "trace buffer full"; @@ -254,6 +257,7 @@ static char *strexcause(uint16_t excause) case 0x2c: return "icplb miss"; case 0x2d: return "multiple icplb hit"; case 0x2e: return "illegal use of supervisor resource"; +#endif default: return "undef"; } } diff --git a/u-boot-2008.10/include/asm-blackfin/blackfin_cdef.h b/u-boot-2008.10/include/asm-blackfin/blackfin_cdef.h index 600349f..61bda24 100644 --- a/u-boot-2008.10/include/asm-blackfin/blackfin_cdef.h +++ b/u-boot-2008.10/include/asm-blackfin/blackfin_cdef.h @@ -81,5 +81,8 @@ #ifdef __ADSPBF561__ # include "mach-bf561/BF561_cdef.h" #endif +#ifdef __ADSPBF579__ +# include "mach-bf579/BF579_cdef.h" +#endif #endif /* __MACH_CDEF_BLACKFIN__ */ diff --git a/u-boot-2008.10/include/asm-blackfin/blackfin_def.h b/u-boot-2008.10/include/asm-blackfin/blackfin_def.h index a7539dd..5cbd348 100644 --- a/u-boot-2008.10/include/asm-blackfin/blackfin_def.h +++ b/u-boot-2008.10/include/asm-blackfin/blackfin_def.h @@ -131,5 +131,10 @@ # include "mach-bf561/anomaly.h" # include "mach-bf561/def_local.h" #endif +#ifdef __ADSPBF579__ +# include "mach-bf579/BF579_def.h" +# include "mach-bf579/anomaly.h" +# include "mach-bf579/def_local.h" +#endif #endif /* __MACH_DEF_BLACKFIN__ */ diff --git a/u-boot-2008.10/include/asm-blackfin/mach-bf579/ADSP-FRIO-core_cdef.h b/u-boot-2008.10/include/asm-blackfin/mach-bf579/ADSP-FRIO-core_cdef.h new file mode 100644 index 0000000..e166a8e --- /dev/null +++ b/u-boot-2008.10/include/asm-blackfin/mach-bf579/ADSP-FRIO-core_cdef.h @@ -0,0 +1,67 @@ +/* DO NOT EDIT THIS FILE + * Automatically generated by generate-cdef-headers.xsl + * DO NOT EDIT THIS FILE + */ + +#ifndef __BFIN_CDEF_ADSP_FRIO_core__ +#define __BFIN_CDEF_ADSP_FRIO_core__ + +#define pWPIACTL ((uint32_t volatile *)WPIACTL) /* Watchpoint control */ +#define bfin_read_WPIACTL() bfin_read32(WPIACTL) +#define bfin_write_WPIACTL(val) bfin_write32(WPIACTL, val) +#define pWPIA0 ((uint32_t volatile *)WPIA0) /* Watchpoint control */ +#define bfin_read_WPIA0() bfin_read32(WPIA0) +#define bfin_write_WPIA0(val) bfin_write32(WPIA0, val) +#define pWPIA1 ((uint32_t volatile *)WPIA1) /* Watchpoint control */ +#define bfin_read_WPIA1() bfin_read32(WPIA1) +#define bfin_write_WPIA1(val) bfin_write32(WPIA1, val) +#define pWPIA2 ((uint32_t volatile *)WPIA2) /* Watchpoint control */ +#define bfin_read_WPIA2() bfin_read32(WPIA2) +#define bfin_write_WPIA2(val) bfin_write32(WPIA2, val) +#define pWPIA3 ((uint32_t volatile *)WPIA3) /* Watchpoint control */ +#define bfin_read_WPIA3() bfin_read32(WPIA3) +#define bfin_write_WPIA3(val) bfin_write32(WPIA3, val) +#define pWPIA4 ((uint32_t volatile *)WPIA4) /* Watchpoint control */ +#define bfin_read_WPIA4() bfin_read32(WPIA4) +#define bfin_write_WPIA4(val) bfin_write32(WPIA4, val) +#define pWPIA5 ((uint32_t volatile *)WPIA5) /* Watchpoint control */ +#define bfin_read_WPIA5() bfin_read32(WPIA5) +#define bfin_write_WPIA5(val) bfin_write32(WPIA5, val) +#define pWPIACNT0 ((uint32_t volatile *)WPIACNT0) /* Watchpoint control */ +#define bfin_read_WPIACNT0() bfin_read32(WPIACNT0) +#define bfin_write_WPIACNT0(val) bfin_write32(WPIACNT0, val) +#define pWPIACNT1 ((uint32_t volatile *)WPIACNT1) /* Watchpoint control */ +#define bfin_read_WPIACNT1() bfin_read32(WPIACNT1) +#define bfin_write_WPIACNT1(val) bfin_write32(WPIACNT1, val) +#define pWPIACNT2 ((uint32_t volatile *)WPIACNT2) /* Watchpoint control */ +#define bfin_read_WPIACNT2() bfin_read32(WPIACNT2) +#define bfin_write_WPIACNT2(val) bfin_write32(WPIACNT2, val) +#define pWPIACNT3 ((uint32_t volatile *)WPIACNT3) /* Watchpoint control */ +#define bfin_read_WPIACNT3() bfin_read32(WPIACNT3) +#define bfin_write_WPIACNT3(val) bfin_write32(WPIACNT3, val) +#define pWPIACNT4 ((uint32_t volatile *)WPIACNT4) /* Watchpoint control */ +#define bfin_read_WPIACNT4() bfin_read32(WPIACNT4) +#define bfin_write_WPIACNT4(val) bfin_write32(WPIACNT4, val) +#define pWPIACNT5 ((uint32_t volatile *)WPIACNT5) /* Watchpoint control */ +#define bfin_read_WPIACNT5() bfin_read32(WPIACNT5) +#define bfin_write_WPIACNT5(val) bfin_write32(WPIACNT5, val) +#define pWPDACTL ((uint32_t volatile *)WPDACTL) /* Watchpoint control */ +#define bfin_read_WPDACTL() bfin_read32(WPDACTL) +#define bfin_write_WPDACTL(val) bfin_write32(WPDACTL, val) +#define pWPDA0 ((uint32_t volatile *)WPDA0) /* Watchpoint control */ +#define bfin_read_WPDA0() bfin_read32(WPDA0) +#define bfin_write_WPDA0(val) bfin_write32(WPDA0, val) +#define pWPDA1 ((uint32_t volatile *)WPDA1) /* Watchpoint control */ +#define bfin_read_WPDA1() bfin_read32(WPDA1) +#define bfin_write_WPDA1(val) bfin_write32(WPDA1, val) +#define pWPDACNT0 ((uint32_t volatile *)WPDACNT0) /* Watchpoint control */ +#define bfin_read_WPDACNT0() bfin_read32(WPDACNT0) +#define bfin_write_WPDACNT0(val) bfin_write32(WPDACNT0, val) +#define pWPDACNT1 ((uint32_t volatile *)WPDACNT1) /* Watchpoint control */ +#define bfin_read_WPDACNT1() bfin_read32(WPDACNT1) +#define bfin_write_WPDACNT1(val) bfin_write32(WPDACNT1, val) +#define pWPSTAT ((uint32_t volatile *)WPSTAT) /* Watchpoint control */ +#define bfin_read_WPSTAT() bfin_read32(WPSTAT) +#define bfin_write_WPSTAT(val) bfin_write32(WPSTAT, val) + +#endif /* __BFIN_CDEF_ADSP_FRIO_core__ */ diff --git a/u-boot-2008.10/include/asm-blackfin/mach-bf579/ADSP-FRIO-core_def.h b/u-boot-2008.10/include/asm-blackfin/mach-bf579/ADSP-FRIO-core_def.h new file mode 100644 index 0000000..8da8542 --- /dev/null +++ b/u-boot-2008.10/include/asm-blackfin/mach-bf579/ADSP-FRIO-core_def.h @@ -0,0 +1,29 @@ +/* DO NOT EDIT THIS FILE + * Automatically generated by generate-def-headers.xsl + * DO NOT EDIT THIS FILE + */ + +#ifndef __BFIN_DEF_ADSP_FRIO_core__ +#define __BFIN_DEF_ADSP_FRIO_core__ + +#define WPIACTL 0xFFE07000 /* Watchpoint control */ +#define WPIA0 0xFFE07040 /* Watchpoint control */ +#define WPIA1 0xFFE07044 /* Watchpoint control */ +#define WPIA2 0xFFE07048 /* Watchpoint control */ +#define WPIA3 0xFFE0704C /* Watchpoint control */ +#define WPIA4 0xFFE07050 /* Watchpoint control */ +#define WPIA5 0xFFE07054 /* Watchpoint control */ +#define WPIACNT0 0xFFE07080 /* Watchpoint control */ +#define WPIACNT1 0xFFE07084 /* Watchpoint control */ +#define WPIACNT2 0xFFE07088 /* Watchpoint control */ +#define WPIACNT3 0xFFE0708C /* Watchpoint control */ +#define WPIACNT4 0xFFE07090 /* Watchpoint control */ +#define WPIACNT5 0xFFE07094 /* Watchpoint control */ +#define WPDACTL 0xFFE07100 /* Watchpoint control */ +#define WPDA0 0xFFE07140 /* Watchpoint control */ +#define WPDA1 0xFFE07144 /* Watchpoint control */ +#define WPDACNT0 0xFFE07180 /* Watchpoint control */ +#define WPDACNT1 0xFFE07184 /* Watchpoint control */ +#define WPSTAT 0xFFE07200 /* Watchpoint control */ + +#endif /* __BFIN_DEF_ADSP_FRIO_core__ */ diff --git a/u-boot-2008.10/include/asm-blackfin/mach-bf579/BF579_cdef.h b/u-boot-2008.10/include/asm-blackfin/mach-bf579/BF579_cdef.h new file mode 100644 index 0000000..a457574 --- /dev/null +++ b/u-boot-2008.10/include/asm-blackfin/mach-bf579/BF579_cdef.h @@ -0,0 +1,1947 @@ +/* DO NOT EDIT THIS FILE + * Automatically generated by generate-cdef-headers.xsl + * DO NOT EDIT THIS FILE + */ + +#ifndef __BFIN_CDEF_ADSP_BF535_proc__ +#define __BFIN_CDEF_ADSP_BF535_proc__ + +#include "ADSP-FRIO-core_cdef.h" + +#define pILAT ((uint16_t volatile *)ILAT) /* Interrupt Latch Register */ +#define bfin_read_ILAT() bfin_read16(ILAT) +#define bfin_write_ILAT(val) bfin_write16(ILAT, val) +#define pIMASK ((uint16_t volatile *)IMASK) /* Interrupt Mask Register */ +#define bfin_read_IMASK() bfin_read16(IMASK) +#define bfin_write_IMASK(val) bfin_write16(IMASK, val) +#define pIPEND ((uint16_t volatile *)IPEND) /* Interrupt Pending Register */ +#define bfin_read_IPEND() bfin_read16(IPEND) +#define bfin_write_IPEND(val) bfin_write16(IPEND, val) +#define pTCNTL ((uint32_t volatile *)TCNTL) +#define bfin_read_TCNTL() bfin_read32(TCNTL) +#define bfin_write_TCNTL(val) bfin_write32(TCNTL, val) +#define pTPERIOD ((uint32_t volatile *)TPERIOD) +#define bfin_read_TPERIOD() bfin_read32(TPERIOD) +#define bfin_write_TPERIOD(val) bfin_write32(TPERIOD, val) +#define pTSCALE ((uint32_t volatile *)TSCALE) +#define bfin_read_TSCALE() bfin_read32(TSCALE) +#define bfin_write_TSCALE(val) bfin_write32(TSCALE, val) +#define pTCOUNT ((uint32_t volatile *)TCOUNT) +#define bfin_read_TCOUNT() bfin_read32(TCOUNT) +#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val) +#define pSRAM_BASE_ADDR ((uint32_t volatile *)SRAM_BASE_ADDR) +#define bfin_read_SRAM_BASE_ADDR() bfin_read32(SRAM_BASE_ADDR) +#define bfin_write_SRAM_BASE_ADDR(val) bfin_write32(SRAM_BASE_ADDR, val) +#define pDMEM_CONTROL ((uint32_t volatile *)DMEM_CONTROL) +#define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL) +#define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL, val) +#define pDCPLB_FAULT_STATUS ((uint32_t volatile *)DCPLB_FAULT_STATUS) +#define bfin_read_DCPLB_FAULT_STATUS() bfin_read32(DCPLB_FAULT_STATUS) +#define bfin_write_DCPLB_FAULT_STATUS(val) bfin_write32(DCPLB_FAULT_STATUS, val) +#define pDCPLB_FAULT_ADDR ((uint32_t volatile *)DCPLB_FAULT_ADDR) +#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR) +#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR, val) +#define pDCPLB_ADDR0 ((uint32_t volatile *)DCPLB_ADDR0) +#define bfin_read_DCPLB_ADDR0() bfin_read32(DCPLB_ADDR0) +#define bfin_write_DCPLB_ADDR0(val) bfin_write32(DCPLB_ADDR0, val) +#define pDCPLB_ADDR1 ((uint32_t volatile *)DCPLB_ADDR1) +#define bfin_read_DCPLB_ADDR1() bfin_read32(DCPLB_ADDR1) +#define bfin_write_DCPLB_ADDR1(val) bfin_write32(DCPLB_ADDR1, val) +#define pDCPLB_ADDR2 ((uint32_t volatile *)DCPLB_ADDR2) +#define bfin_read_DCPLB_ADDR2() bfin_read32(DCPLB_ADDR2) +#define bfin_write_DCPLB_ADDR2(val) bfin_write32(DCPLB_ADDR2, val) +#define pDCPLB_ADDR3 ((uint32_t volatile *)DCPLB_ADDR3) +#define bfin_read_DCPLB_ADDR3() bfin_read32(DCPLB_ADDR3) +#define bfin_write_DCPLB_ADDR3(val) bfin_write32(DCPLB_ADDR3, val) +#define pDCPLB_ADDR4 ((uint32_t volatile *)DCPLB_ADDR4) +#define bfin_read_DCPLB_ADDR4() bfin_read32(DCPLB_ADDR4) +#define bfin_write_DCPLB_ADDR4(val) bfin_write32(DCPLB_ADDR4, val) +#define pDCPLB_ADDR5 ((uint32_t volatile *)DCPLB_ADDR5) +#define bfin_read_DCPLB_ADDR5() bfin_read32(DCPLB_ADDR5) +#define bfin_write_DCPLB_ADDR5(val) bfin_write32(DCPLB_ADDR5, val) +#define pDCPLB_ADDR6 ((uint32_t volatile *)DCPLB_ADDR6) +#define bfin_read_DCPLB_ADDR6() bfin_read32(DCPLB_ADDR6) +#define bfin_write_DCPLB_ADDR6(val) bfin_write32(DCPLB_ADDR6, val) +#define pDCPLB_ADDR7 ((uint32_t volatile *)DCPLB_ADDR7) +#define bfin_read_DCPLB_ADDR7() bfin_read32(DCPLB_ADDR7) +#define bfin_write_DCPLB_ADDR7(val) bfin_write32(DCPLB_ADDR7, val) +#define pDCPLB_ADDR8 ((uint32_t volatile *)DCPLB_ADDR8) +#define bfin_read_DCPLB_ADDR8() bfin_read32(DCPLB_ADDR8) +#define bfin_write_DCPLB_ADDR8(val) bfin_write32(DCPLB_ADDR8, val) +#define pDCPLB_ADDR9 ((uint32_t volatile *)DCPLB_ADDR9) +#define bfin_read_DCPLB_ADDR9() bfin_read32(DCPLB_ADDR9) +#define bfin_write_DCPLB_ADDR9(val) bfin_write32(DCPLB_ADDR9, val) +#define pDCPLB_ADDR10 ((uint32_t volatile *)DCPLB_ADDR10) +#define bfin_read_DCPLB_ADDR10() bfin_read32(DCPLB_ADDR10) +#define bfin_write_DCPLB_ADDR10(val) bfin_write32(DCPLB_ADDR10, val) +#define pDCPLB_ADDR11 ((uint32_t volatile *)DCPLB_ADDR11) +#define bfin_read_DCPLB_ADDR11() bfin_read32(DCPLB_ADDR11) +#define bfin_write_DCPLB_ADDR11(val) bfin_write32(DCPLB_ADDR11, val) +#define pDCPLB_ADDR12 ((uint32_t volatile *)DCPLB_ADDR12) +#define bfin_read_DCPLB_ADDR12() bfin_read32(DCPLB_ADDR12) +#define bfin_write_DCPLB_ADDR12(val) bfin_write32(DCPLB_ADDR12, val) +#define pDCPLB_ADDR13 ((uint32_t volatile *)DCPLB_ADDR13) +#define bfin_read_DCPLB_ADDR13() bfin_read32(DCPLB_ADDR13) +#define bfin_write_DCPLB_ADDR13(val) bfin_write32(DCPLB_ADDR13, val) +#define pDCPLB_ADDR14 ((uint32_t volatile *)DCPLB_ADDR14) +#define bfin_read_DCPLB_ADDR14() bfin_read32(DCPLB_ADDR14) +#define bfin_write_DCPLB_ADDR14(val) bfin_write32(DCPLB_ADDR14, val) +#define pDCPLB_ADDR15 ((uint32_t volatile *)DCPLB_ADDR15) +#define bfin_read_DCPLB_ADDR15() bfin_read32(DCPLB_ADDR15) +#define bfin_write_DCPLB_ADDR15(val) bfin_write32(DCPLB_ADDR15, val) +#define pDCPLB_DATA0 ((uint32_t volatile *)DCPLB_DATA0) +#define bfin_read_DCPLB_DATA0() bfin_read32(DCPLB_DATA0) +#define bfin_write_DCPLB_DATA0(val) bfin_write32(DCPLB_DATA0, val) +#define pDCPLB_DATA1 ((uint32_t volatile *)DCPLB_DATA1) +#define bfin_read_DCPLB_DATA1() bfin_read32(DCPLB_DATA1) +#define bfin_write_DCPLB_DATA1(val) bfin_write32(DCPLB_DATA1, val) +#define pDCPLB_DATA2 ((uint32_t volatile *)DCPLB_DATA2) +#define bfin_read_DCPLB_DATA2() bfin_read32(DCPLB_DATA2) +#define bfin_write_DCPLB_DATA2(val) bfin_write32(DCPLB_DATA2, val) +#define pDCPLB_DATA3 ((uint32_t volatile *)DCPLB_DATA3) +#define bfin_read_DCPLB_DATA3() bfin_read32(DCPLB_DATA3) +#define bfin_write_DCPLB_DATA3(val) bfin_write32(DCPLB_DATA3, val) +#define pDCPLB_DATA4 ((uint32_t volatile *)DCPLB_DATA4) +#define bfin_read_DCPLB_DATA4() bfin_read32(DCPLB_DATA4) +#define bfin_write_DCPLB_DATA4(val) bfin_write32(DCPLB_DATA4, val) +#define pDCPLB_DATA5 ((uint32_t volatile *)DCPLB_DATA5) +#define bfin_read_DCPLB_DATA5() bfin_read32(DCPLB_DATA5) +#define bfin_write_DCPLB_DATA5(val) bfin_write32(DCPLB_DATA5, val) +#define pDCPLB_DATA6 ((uint32_t volatile *)DCPLB_DATA6) +#define bfin_read_DCPLB_DATA6() bfin_read32(DCPLB_DATA6) +#define bfin_write_DCPLB_DATA6(val) bfin_write32(DCPLB_DATA6, val) +#define pDCPLB_DATA7 ((uint32_t volatile *)DCPLB_DATA7) +#define bfin_read_DCPLB_DATA7() bfin_read32(DCPLB_DATA7) +#define bfin_write_DCPLB_DATA7(val) bfin_write32(DCPLB_DATA7, val) +#define pDCPLB_DATA8 ((uint32_t volatile *)DCPLB_DATA8) +#define bfin_read_DCPLB_DATA8() bfin_read32(DCPLB_DATA8) +#define bfin_write_DCPLB_DATA8(val) bfin_write32(DCPLB_DATA8, val) +#define pDCPLB_DATA9 ((uint32_t volatile *)DCPLB_DATA9) +#define bfin_read_DCPLB_DATA9() bfin_read32(DCPLB_DATA9) +#define bfin_write_DCPLB_DATA9(val) bfin_write32(DCPLB_DATA9, val) +#define pDCPLB_DATA10 ((uint32_t volatile *)DCPLB_DATA10) +#define bfin_read_DCPLB_DATA10() bfin_read32(DCPLB_DATA10) +#define bfin_write_DCPLB_DATA10(val) bfin_write32(DCPLB_DATA10, val) +#define pDCPLB_DATA11 ((uint32_t volatile *)DCPLB_DATA11) +#define bfin_read_DCPLB_DATA11() bfin_read32(DCPLB_DATA11) +#define bfin_write_DCPLB_DATA11(val) bfin_write32(DCPLB_DATA11, val) +#define pDCPLB_DATA12 ((uint32_t volatile *)DCPLB_DATA12) +#define bfin_read_DCPLB_DATA12() bfin_read32(DCPLB_DATA12) +#define bfin_write_DCPLB_DATA12(val) bfin_write32(DCPLB_DATA12, val) +#define pDCPLB_DATA13 ((uint32_t volatile *)DCPLB_DATA13) +#define bfin_read_DCPLB_DATA13() bfin_read32(DCPLB_DATA13) +#define bfin_write_DCPLB_DATA13(val) bfin_write32(DCPLB_DATA13, val) +#define pDCPLB_DATA14 ((uint32_t volatile *)DCPLB_DATA14) +#define bfin_read_DCPLB_DATA14() bfin_read32(DCPLB_DATA14) +#define bfin_write_DCPLB_DATA14(val) bfin_write32(DCPLB_DATA14, val) +#define pDCPLB_DATA15 ((uint32_t volatile *)DCPLB_DATA15) +#define bfin_read_DCPLB_DATA15() bfin_read32(DCPLB_DATA15) +#define bfin_write_DCPLB_DATA15(val) bfin_write32(DCPLB_DATA15, val) +#define pDTEST_COMMAND ((uint32_t volatile *)DTEST_COMMAND) +#define bfin_read_DTEST_COMMAND() bfin_read32(DTEST_COMMAND) +#define bfin_write_DTEST_COMMAND(val) bfin_write32(DTEST_COMMAND, val) +#define pDTEST_DATA0 ((uint32_t volatile *)DTEST_DATA0) +#define bfin_read_DTEST_DATA0() bfin_read32(DTEST_DATA0) +#define bfin_write_DTEST_DATA0(val) bfin_write32(DTEST_DATA0, val) +#define pDTEST_DATA1 ((uint32_t volatile *)DTEST_DATA1) +#define bfin_read_DTEST_DATA1() bfin_read32(DTEST_DATA1) +#define bfin_write_DTEST_DATA1(val) bfin_write32(DTEST_DATA1, val) +#define pEVT0 ((uint32_t volatile *)EVT0) +#define bfin_read_EVT0() bfin_read32(EVT0) +#define bfin_write_EVT0(val) bfin_write32(EVT0, val) +#define pEVT1 ((uint32_t volatile *)EVT1) +#define bfin_read_EVT1() bfin_read32(EVT1) +#define bfin_write_EVT1(val) bfin_write32(EVT1, val) +#define pEVT2 ((uint32_t volatile *)EVT2) +#define bfin_read_EVT2() bfin_read32(EVT2) +#define bfin_write_EVT2(val) bfin_write32(EVT2, val) +#define pEVT3 ((uint32_t volatile *)EVT3) +#define bfin_read_EVT3() bfin_read32(EVT3) +#define bfin_write_EVT3(val) bfin_write32(EVT3, val) +#define pEVT4 ((uint32_t volatile *)EVT4) +#define bfin_read_EVT4() bfin_read32(EVT4) +#define bfin_write_EVT4(val) bfin_write32(EVT4, val) +#define pEVT5 ((uint32_t volatile *)EVT5) +#define bfin_read_EVT5() bfin_read32(EVT5) +#define bfin_write_EVT5(val) bfin_write32(EVT5, val) +#define pEVT6 ((uint32_t volatile *)EVT6) +#define bfin_read_EVT6() bfin_read32(EVT6) +#define bfin_write_EVT6(val) bfin_write32(EVT6, val) +#define pEVT7 ((uint32_t volatile *)EVT7) +#define bfin_read_EVT7() bfin_read32(EVT7) +#define bfin_write_EVT7(val) bfin_write32(EVT7, val) +#define pEVT8 ((uint32_t volatile *)EVT8) +#define bfin_read_EVT8() bfin_read32(EVT8) +#define bfin_write_EVT8(val) bfin_write32(EVT8, val) +#define pEVT9 ((uint32_t volatile *)EVT9) +#define bfin_read_EVT9() bfin_read32(EVT9) +#define bfin_write_EVT9(val) bfin_write32(EVT9, val) +#define pEVT10 ((uint32_t volatile *)EVT10) +#define bfin_read_EVT10() bfin_read32(EVT10) +#define bfin_write_EVT10(val) bfin_write32(EVT10, val) +#define pEVT11 ((uint32_t volatile *)EVT11) +#define bfin_read_EVT11() bfin_read32(EVT11) +#define bfin_write_EVT11(val) bfin_write32(EVT11, val) +#define pEVT12 ((uint32_t volatile *)EVT12) +#define bfin_read_EVT12() bfin_read32(EVT12) +#define bfin_write_EVT12(val) bfin_write32(EVT12, val) +#define pEVT13 ((uint32_t volatile *)EVT13) +#define bfin_read_EVT13() bfin_read32(EVT13) +#define bfin_write_EVT13(val) bfin_write32(EVT13, val) +#define pEVT14 ((uint32_t volatile *)EVT14) +#define bfin_read_EVT14() bfin_read32(EVT14) +#define bfin_write_EVT14(val) bfin_write32(EVT14, val) +#define pEVT15 ((uint32_t volatile *)EVT15) +#define bfin_read_EVT15() bfin_read32(EVT15) +#define bfin_write_EVT15(val) bfin_write32(EVT15, val) +#define pIMEM_CONTROL ((uint32_t volatile *)IMEM_CONTROL) +#define bfin_read_IMEM_CONTROL() bfin_read32(IMEM_CONTROL) +#define bfin_write_IMEM_CONTROL(val) bfin_write32(IMEM_CONTROL, val) +#define pICPLB_FAULT_STATUS ((uint32_t volatile *)ICPLB_FAULT_STATUS) +#define bfin_read_ICPLB_FAULT_STATUS() bfin_read32(ICPLB_FAULT_STATUS) +#define bfin_write_ICPLB_FAULT_STATUS(val) bfin_write32(ICPLB_FAULT_STATUS, val) +#define pICPLB_FAULT_ADDR ((uint32_t volatile *)ICPLB_FAULT_ADDR) +#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR) +#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR, val) +#define pICPLB_ADDR0 ((uint32_t volatile *)ICPLB_ADDR0) +#define bfin_read_ICPLB_ADDR0() bfin_read32(ICPLB_ADDR0) +#define bfin_write_ICPLB_ADDR0(val) bfin_write32(ICPLB_ADDR0, val) +#define pICPLB_ADDR1 ((uint32_t volatile *)ICPLB_ADDR1) +#define bfin_read_ICPLB_ADDR1() bfin_read32(ICPLB_ADDR1) +#define bfin_write_ICPLB_ADDR1(val) bfin_write32(ICPLB_ADDR1, val) +#define pICPLB_ADDR2 ((uint32_t volatile *)ICPLB_ADDR2) +#define bfin_read_ICPLB_ADDR2() bfin_read32(ICPLB_ADDR2) +#define bfin_write_ICPLB_ADDR2(val) bfin_write32(ICPLB_ADDR2, val) +#define pICPLB_ADDR3 ((uint32_t volatile *)ICPLB_ADDR3) +#define bfin_read_ICPLB_ADDR3() bfin_read32(ICPLB_ADDR3) +#define bfin_write_ICPLB_ADDR3(val) bfin_write32(ICPLB_ADDR3, val) +#define pICPLB_ADDR4 ((uint32_t volatile *)ICPLB_ADDR4) +#define bfin_read_ICPLB_ADDR4() bfin_read32(ICPLB_ADDR4) +#define bfin_write_ICPLB_ADDR4(val) bfin_write32(ICPLB_ADDR4, val) +#define pICPLB_ADDR5 ((uint32_t volatile *)ICPLB_ADDR5) +#define bfin_read_ICPLB_ADDR5() bfin_read32(ICPLB_ADDR5) +#define bfin_write_ICPLB_ADDR5(val) bfin_write32(ICPLB_ADDR5, val) +#define pICPLB_ADDR6 ((uint32_t volatile *)ICPLB_ADDR6) +#define bfin_read_ICPLB_ADDR6() bfin_read32(ICPLB_ADDR6) +#define bfin_write_ICPLB_ADDR6(val) bfin_write32(ICPLB_ADDR6, val) +#define pICPLB_ADDR7 ((uint32_t volatile *)ICPLB_ADDR7) +#define bfin_read_ICPLB_ADDR7() bfin_read32(ICPLB_ADDR7) +#define bfin_write_ICPLB_ADDR7(val) bfin_write32(ICPLB_ADDR7, val) +#define pICPLB_ADDR8 ((uint32_t volatile *)ICPLB_ADDR8) +#define bfin_read_ICPLB_ADDR8() bfin_read32(ICPLB_ADDR8) +#define bfin_write_ICPLB_ADDR8(val) bfin_write32(ICPLB_ADDR8, val) +#define pICPLB_ADDR9 ((uint32_t volatile *)ICPLB_ADDR9) +#define bfin_read_ICPLB_ADDR9() bfin_read32(ICPLB_ADDR9) +#define bfin_write_ICPLB_ADDR9(val) bfin_write32(ICPLB_ADDR9, val) +#define pICPLB_ADDR10 ((uint32_t volatile *)ICPLB_ADDR10) +#define bfin_read_ICPLB_ADDR10() bfin_read32(ICPLB_ADDR10) +#define bfin_write_ICPLB_ADDR10(val) bfin_write32(ICPLB_ADDR10, val) +#define pICPLB_ADDR11 ((uint32_t volatile *)ICPLB_ADDR11) +#define bfin_read_ICPLB_ADDR11() bfin_read32(ICPLB_ADDR11) +#define bfin_write_ICPLB_ADDR11(val) bfin_write32(ICPLB_ADDR11, val) +#define pICPLB_ADDR12 ((uint32_t volatile *)ICPLB_ADDR12) +#define bfin_read_ICPLB_ADDR12() bfin_read32(ICPLB_ADDR12) +#define bfin_write_ICPLB_ADDR12(val) bfin_write32(ICPLB_ADDR12, val) +#define pICPLB_ADDR13 ((uint32_t volatile *)ICPLB_ADDR13) +#define bfin_read_ICPLB_ADDR13() bfin_read32(ICPLB_ADDR13) +#define bfin_write_ICPLB_ADDR13(val) bfin_write32(ICPLB_ADDR13, val) +#define pICPLB_ADDR14 ((uint32_t volatile *)ICPLB_ADDR14) +#define bfin_read_ICPLB_ADDR14() bfin_read32(ICPLB_ADDR14) +#define bfin_write_ICPLB_ADDR14(val) bfin_write32(ICPLB_ADDR14, val) +#define pICPLB_ADDR15 ((uint32_t volatile *)ICPLB_ADDR15) +#define bfin_read_ICPLB_ADDR15() bfin_read32(ICPLB_ADDR15) +#define bfin_write_ICPLB_ADDR15(val) bfin_write32(ICPLB_ADDR15, val) +#define pICPLB_DATA0 ((uint32_t volatile *)ICPLB_DATA0) +#define bfin_read_ICPLB_DATA0() bfin_read32(ICPLB_DATA0) +#define bfin_write_ICPLB_DATA0(val) bfin_write32(ICPLB_DATA0, val) +#define pICPLB_DATA1 ((uint32_t volatile *)ICPLB_DATA1) +#define bfin_read_ICPLB_DATA1() bfin_read32(ICPLB_DATA1) +#define bfin_write_ICPLB_DATA1(val) bfin_write32(ICPLB_DATA1, val) +#define pICPLB_DATA2 ((uint32_t volatile *)ICPLB_DATA2) +#define bfin_read_ICPLB_DATA2() bfin_read32(ICPLB_DATA2) +#define bfin_write_ICPLB_DATA2(val) bfin_write32(ICPLB_DATA2, val) +#define pICPLB_DATA3 ((uint32_t volatile *)ICPLB_DATA3) +#define bfin_read_ICPLB_DATA3() bfin_read32(ICPLB_DATA3) +#define bfin_write_ICPLB_DATA3(val) bfin_write32(ICPLB_DATA3, val) +#define pICPLB_DATA4 ((uint32_t volatile *)ICPLB_DATA4) +#define bfin_read_ICPLB_DATA4() bfin_read32(ICPLB_DATA4) +#define bfin_write_ICPLB_DATA4(val) bfin_write32(ICPLB_DATA4, val) +#define pICPLB_DATA5 ((uint32_t volatile *)ICPLB_DATA5) +#define bfin_read_ICPLB_DATA5() bfin_read32(ICPLB_DATA5) +#define bfin_write_ICPLB_DATA5(val) bfin_write32(ICPLB_DATA5, val) +#define pICPLB_DATA6 ((uint32_t volatile *)ICPLB_DATA6) +#define bfin_read_ICPLB_DATA6() bfin_read32(ICPLB_DATA6) +#define bfin_write_ICPLB_DATA6(val) bfin_write32(ICPLB_DATA6, val) +#define pICPLB_DATA7 ((uint32_t volatile *)ICPLB_DATA7) +#define bfin_read_ICPLB_DATA7() bfin_read32(ICPLB_DATA7) +#define bfin_write_ICPLB_DATA7(val) bfin_write32(ICPLB_DATA7, val) +#define pICPLB_DATA8 ((uint32_t volatile *)ICPLB_DATA8) +#define bfin_read_ICPLB_DATA8() bfin_read32(ICPLB_DATA8) +#define bfin_write_ICPLB_DATA8(val) bfin_write32(ICPLB_DATA8, val) +#define pICPLB_DATA9 ((uint32_t volatile *)ICPLB_DATA9) +#define bfin_read_ICPLB_DATA9() bfin_read32(ICPLB_DATA9) +#define bfin_write_ICPLB_DATA9(val) bfin_write32(ICPLB_DATA9, val) +#define pICPLB_DATA10 ((uint32_t volatile *)ICPLB_DATA10) +#define bfin_read_ICPLB_DATA10() bfin_read32(ICPLB_DATA10) +#define bfin_write_ICPLB_DATA10(val) bfin_write32(ICPLB_DATA10, val) +#define pICPLB_DATA11 ((uint32_t volatile *)ICPLB_DATA11) +#define bfin_read_ICPLB_DATA11() bfin_read32(ICPLB_DATA11) +#define bfin_write_ICPLB_DATA11(val) bfin_write32(ICPLB_DATA11, val) +#define pICPLB_DATA12 ((uint32_t volatile *)ICPLB_DATA12) +#define bfin_read_ICPLB_DATA12() bfin_read32(ICPLB_DATA12) +#define bfin_write_ICPLB_DATA12(val) bfin_write32(ICPLB_DATA12, val) +#define pICPLB_DATA13 ((uint32_t volatile *)ICPLB_DATA13) +#define bfin_read_ICPLB_DATA13() bfin_read32(ICPLB_DATA13) +#define bfin_write_ICPLB_DATA13(val) bfin_write32(ICPLB_DATA13, val) +#define pICPLB_DATA14 ((uint32_t volatile *)ICPLB_DATA14) +#define bfin_read_ICPLB_DATA14() bfin_read32(ICPLB_DATA14) +#define bfin_write_ICPLB_DATA14(val) bfin_write32(ICPLB_DATA14, val) +#define pICPLB_DATA15 ((uint32_t volatile *)ICPLB_DATA15) +#define bfin_read_ICPLB_DATA15() bfin_read32(ICPLB_DATA15) +#define bfin_write_ICPLB_DATA15(val) bfin_write32(ICPLB_DATA15, val) +#define pITEST_COMMAND ((uint32_t volatile *)ITEST_COMMAND) +#define bfin_read_ITEST_COMMAND() bfin_read32(ITEST_COMMAND) +#define bfin_write_ITEST_COMMAND(val) bfin_write32(ITEST_COMMAND, val) +#define pITEST_DATA0 ((uint32_t volatile *)ITEST_DATA0) +#define bfin_read_ITEST_DATA0() bfin_read32(ITEST_DATA0) +#define bfin_write_ITEST_DATA0(val) bfin_write32(ITEST_DATA0, val) +#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1) +#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1) +#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val) +#define pSPT0_TX_CONFIG ((uint16_t volatile *)SPT0_TX_CONFIG) +#define bfin_read_SPT0_TX_CONFIG() bfin_read16(SPT0_TX_CONFIG) +#define bfin_write_SPT0_TX_CONFIG(val) bfin_write16(SPT0_TX_CONFIG, val) +#define pSPT0_RX_CONFIG ((uint16_t volatile *)SPT0_RX_CONFIG) +#define bfin_read_SPT0_RX_CONFIG() bfin_read16(SPT0_RX_CONFIG) +#define bfin_write_SPT0_RX_CONFIG(val) bfin_write16(SPT0_RX_CONFIG, val) +#define pSPT0_TX ((uint32_t volatile *)SPT0_TX) +#define bfin_read_SPT0_TX() bfin_read32(SPT0_TX) +#define bfin_write_SPT0_TX(val) bfin_write32(SPT0_TX, val) +#define pSPT0_RX ((uint32_t volatile *)SPT0_RX) +#define bfin_read_SPT0_RX() bfin_read32(SPT0_RX) +#define bfin_write_SPT0_RX(val) bfin_write32(SPT0_RX, val) +#define pSPT0_TSCLKDIV ((uint16_t volatile *)SPT0_TSCLKDIV) +#define bfin_read_SPT0_TSCLKDIV() bfin_read16(SPT0_TSCLKDIV) +#define bfin_write_SPT0_TSCLKDIV(val) bfin_write16(SPT0_TSCLKDIV, val) +#define pSPT0_RSCLKDIV ((uint16_t volatile *)SPT0_RSCLKDIV) +#define bfin_read_SPT0_RSCLKDIV() bfin_read16(SPT0_RSCLKDIV) +#define bfin_write_SPT0_RSCLKDIV(val) bfin_write16(SPT0_RSCLKDIV, val) +#define pSPT0_TFSDIV ((uint16_t volatile *)SPT0_TFSDIV) +#define bfin_read_SPT0_TFSDIV() bfin_read16(SPT0_TFSDIV) +#define bfin_write_SPT0_TFSDIV(val) bfin_write16(SPT0_TFSDIV, val) +#define pSPT0_RFSDIV ((uint16_t volatile *)SPT0_RFSDIV) +#define bfin_read_SPT0_RFSDIV() bfin_read16(SPT0_RFSDIV) +#define bfin_write_SPT0_RFSDIV(val) bfin_write16(SPT0_RFSDIV, val) +#define pSPT0_STAT ((uint16_t volatile *)SPT0_STAT) +#define bfin_read_SPT0_STAT() bfin_read16(SPT0_STAT) +#define bfin_write_SPT0_STAT(val) bfin_write16(SPT0_STAT, val) +#define pSPT0_MTCS0 ((uint32_t volatile *)SPT0_MTCS0) +#define bfin_read_SPT0_MTCS0() bfin_read32(SPT0_MTCS0) +#define bfin_write_SPT0_MTCS0(val) bfin_write32(SPT0_MTCS0, val) +#define pSPT0_MTCS1 ((uint32_t volatile *)SPT0_MTCS1) +#define bfin_read_SPT0_MTCS1() bfin_read32(SPT0_MTCS1) +#define bfin_write_SPT0_MTCS1(val) bfin_write32(SPT0_MTCS1, val) +#define pSPT0_MTCS2 ((uint32_t volatile *)SPT0_MTCS2) +#define bfin_read_SPT0_MTCS2() bfin_read32(SPT0_MTCS2) +#define bfin_write_SPT0_MTCS2(val) bfin_write32(SPT0_MTCS2, val) +#define pSPT0_MTCS3 ((uint32_t volatile *)SPT0_MTCS3) +#define bfin_read_SPT0_MTCS3() bfin_read32(SPT0_MTCS3) +#define bfin_write_SPT0_MTCS3(val) bfin_write32(SPT0_MTCS3, val) +#define pSPT0_MTCS4 ((uint16_t volatile *)SPT0_MTCS4) +#define bfin_read_SPT0_MTCS4() bfin_read16(SPT0_MTCS4) +#define bfin_write_SPT0_MTCS4(val) bfin_write16(SPT0_MTCS4, val) +#define pSPT0_MTCS5 ((uint16_t volatile *)SPT0_MTCS5) +#define bfin_read_SPT0_MTCS5() bfin_read16(SPT0_MTCS5) +#define bfin_write_SPT0_MTCS5(val) bfin_write16(SPT0_MTCS5, val) +#define pSPT0_MTCS6 ((uint16_t volatile *)SPT0_MTCS6) +#define bfin_read_SPT0_MTCS6() bfin_read16(SPT0_MTCS6) +#define bfin_write_SPT0_MTCS6(val) bfin_write16(SPT0_MTCS6, val) +#define pSPT0_MTCS7 ((uint16_t volatile *)SPT0_MTCS7) +#define bfin_read_SPT0_MTCS7() bfin_read16(SPT0_MTCS7) +#define bfin_write_SPT0_MTCS7(val) bfin_write16(SPT0_MTCS7, val) +#define pSPT0_MRCS0 ((uint32_t volatile *)SPT0_MRCS0) +#define bfin_read_SPT0_MRCS0() bfin_read32(SPT0_MRCS0) +#define bfin_write_SPT0_MRCS0(val) bfin_write32(SPT0_MRCS0, val) +#define pSPT0_MRCS1 ((uint32_t volatile *)SPT0_MRCS1) +#define bfin_read_SPT0_MRCS1() bfin_read32(SPT0_MRCS1) +#define bfin_write_SPT0_MRCS1(val) bfin_write32(SPT0_MRCS1, val) +#define pSPT0_MRCS2 ((uint32_t volatile *)SPT0_MRCS2) +#define bfin_read_SPT0_MRCS2() bfin_read32(SPT0_MRCS2) +#define bfin_write_SPT0_MRCS2(val) bfin_write32(SPT0_MRCS2, val) +#define pSPT0_MRCS3 ((uint32_t volatile *)SPT0_MRCS3) +#define bfin_read_SPT0_MRCS3() bfin_read32(SPT0_MRCS3) +#define bfin_write_SPT0_MRCS3(val) bfin_write32(SPT0_MRCS3, val) +#define pSPT0_MRCS4 ((uint16_t volatile *)SPT0_MRCS4) +#define bfin_read_SPT0_MRCS4() bfin_read16(SPT0_MRCS4) +#define bfin_write_SPT0_MRCS4(val) bfin_write16(SPT0_MRCS4, val) +#define pSPT0_MRCS5 ((uint16_t volatile *)SPT0_MRCS5) +#define bfin_read_SPT0_MRCS5() bfin_read16(SPT0_MRCS5) +#define bfin_write_SPT0_MRCS5(val) bfin_write16(SPT0_MRCS5, val) +#define pSPT0_MRCS6 ((uint16_t volatile *)SPT0_MRCS6) +#define bfin_read_SPT0_MRCS6() bfin_read16(SPT0_MRCS6) +#define bfin_write_SPT0_MRCS6(val) bfin_write16(SPT0_MRCS6, val) +#define pSPT0_MRCS7 ((uint16_t volatile *)SPT0_MRCS7) +#define bfin_read_SPT0_MRCS7() bfin_read16(SPT0_MRCS7) +#define bfin_write_SPT0_MRCS7(val) bfin_write16(SPT0_MRCS7, val) +#define pSPT0_MCMC1 ((uint16_t volatile *)SPT0_MCMC1) +#define bfin_read_SPT0_MCMC1() bfin_read16(SPT0_MCMC1) +#define bfin_write_SPT0_MCMC1(val) bfin_write16(SPT0_MCMC1, val) +#define pSPT0_MCMC2 ((uint16_t volatile *)SPT0_MCMC2) +#define bfin_read_SPT0_MCMC2() bfin_read16(SPT0_MCMC2) +#define bfin_write_SPT0_MCMC2(val) bfin_write16(SPT0_MCMC2, val) +#define pSPT0_RX_CURR_PTR ((uint16_t volatile *)SPT0_RX_CURR_PTR) +#define bfin_read_SPT0_RX_CURR_PTR() bfin_read16(SPT0_RX_CURR_PTR) +#define bfin_write_SPT0_RX_CURR_PTR(val) bfin_write16(SPT0_RX_CURR_PTR, val) +#define pSPT0_RX_CONFIG_DMA ((uint16_t volatile *)SPT0_RX_CONFIG_DMA) +#define bfin_read_SPT0_RX_CONFIG_DMA() bfin_read16(SPT0_RX_CONFIG_DMA) +#define bfin_write_SPT0_RX_CONFIG_DMA(val) bfin_write16(SPT0_RX_CONFIG_DMA, val) +#define pSPT0_RX_START_PG ((uint16_t volatile *)SPT0_RX_START_PG) +#define bfin_read_SPT0_RX_START_PG() bfin_read16(SPT0_RX_START_PG) +#define bfin_write_SPT0_RX_START_PG(val) bfin_write16(SPT0_RX_START_PG, val) +#define pSPT0_RX_START_ADDR ((uint16_t volatile *)SPT0_RX_START_ADDR) +#define bfin_read_SPT0_RX_START_ADDR() bfin_read16(SPT0_RX_START_ADDR) +#define bfin_write_SPT0_RX_START_ADDR(val) bfin_write16(SPT0_RX_START_ADDR, val) +#define pSPT0_RX_COUNT ((uint16_t volatile *)SPT0_RX_COUNT) +#define bfin_read_SPT0_RX_COUNT() bfin_read16(SPT0_RX_COUNT) +#define bfin_write_SPT0_RX_COUNT(val) bfin_write16(SPT0_RX_COUNT, val) +#define pSPT0_RX_NEXT_DESCR ((uint16_t volatile *)SPT0_RX_NEXT_DESCR) +#define bfin_read_SPT0_RX_NEXT_DESCR() bfin_read16(SPT0_RX_NEXT_DESCR) +#define bfin_write_SPT0_RX_NEXT_DESCR(val) bfin_write16(SPT0_RX_NEXT_DESCR, val) +#define pSPT0_RX_DESCR_RDY ((uint16_t volatile *)SPT0_RX_DESCR_RDY) +#define bfin_read_SPT0_RX_DESCR_RDY() bfin_read16(SPT0_RX_DESCR_RDY) +#define bfin_write_SPT0_RX_DESCR_RDY(val) bfin_write16(SPT0_RX_DESCR_RDY, val) +#define pSPT0_RX_IRQSTAT ((uint16_t volatile *)SPT0_RX_IRQSTAT) +#define bfin_read_SPT0_RX_IRQSTAT() bfin_read16(SPT0_RX_IRQSTAT) +#define bfin_write_SPT0_RX_IRQSTAT(val) bfin_write16(SPT0_RX_IRQSTAT, val) +#define pSPT0_TX_CURR_PTR ((uint16_t volatile *)SPT0_TX_CURR_PTR) +#define bfin_read_SPT0_TX_CURR_PTR() bfin_read16(SPT0_TX_CURR_PTR) +#define bfin_write_SPT0_TX_CURR_PTR(val) bfin_write16(SPT0_TX_CURR_PTR, val) +#define pSPT0_TX_CONFIG_DMA ((uint16_t volatile *)SPT0_TX_CONFIG_DMA) +#define bfin_read_SPT0_TX_CONFIG_DMA() bfin_read16(SPT0_TX_CONFIG_DMA) +#define bfin_write_SPT0_TX_CONFIG_DMA(val) bfin_write16(SPT0_TX_CONFIG_DMA, val) +#define pSPT0_TX_START_PG ((uint16_t volatile *)SPT0_TX_START_PG) +#define bfin_read_SPT0_TX_START_PG() bfin_read16(SPT0_TX_START_PG) +#define bfin_write_SPT0_TX_START_PG(val) bfin_write16(SPT0_TX_START_PG, val) +#define pSPT0_TX_START_ADDR ((uint16_t volatile *)SPT0_TX_START_ADDR) +#define bfin_read_SPT0_TX_START_ADDR() bfin_read16(SPT0_TX_START_ADDR) +#define bfin_write_SPT0_TX_START_ADDR(val) bfin_write16(SPT0_TX_START_ADDR, val) +#define pSPT0_TX_COUNT ((uint16_t volatile *)SPT0_TX_COUNT) +#define bfin_read_SPT0_TX_COUNT() bfin_read16(SPT0_TX_COUNT) +#define bfin_write_SPT0_TX_COUNT(val) bfin_write16(SPT0_TX_COUNT, val) +#define pSPT0_TX_NEXT_DESCR ((uint16_t volatile *)SPT0_TX_NEXT_DESCR) +#define bfin_read_SPT0_TX_NEXT_DESCR() bfin_read16(SPT0_TX_NEXT_DESCR) +#define bfin_write_SPT0_TX_NEXT_DESCR(val) bfin_write16(SPT0_TX_NEXT_DESCR, val) +#define pSPT0_TX_DESCR_RDY ((uint16_t volatile *)SPT0_TX_DESCR_RDY) +#define bfin_read_SPT0_TX_DESCR_RDY() bfin_read16(SPT0_TX_DESCR_RDY) +#define bfin_write_SPT0_TX_DESCR_RDY(val) bfin_write16(SPT0_TX_DESCR_RDY, val) +#define pSPT0_TX_IRQSTAT ((uint16_t volatile *)SPT0_TX_IRQSTAT) +#define bfin_read_SPT0_TX_IRQSTAT() bfin_read16(SPT0_TX_IRQSTAT) +#define bfin_write_SPT0_TX_IRQSTAT(val) bfin_write16(SPT0_TX_IRQSTAT, val) +#define pSPT1_TX_CONFIG ((uint16_t volatile *)SPT1_TX_CONFIG) +#define bfin_read_SPT1_TX_CONFIG() bfin_read16(SPT1_TX_CONFIG) +#define bfin_write_SPT1_TX_CONFIG(val) bfin_write16(SPT1_TX_CONFIG, val) +#define pSPT1_RX_CONFIG ((uint16_t volatile *)SPT1_RX_CONFIG) +#define bfin_read_SPT1_RX_CONFIG() bfin_read16(SPT1_RX_CONFIG) +#define bfin_write_SPT1_RX_CONFIG(val) bfin_write16(SPT1_RX_CONFIG, val) +#define pSPT1_TX ((uint16_t volatile *)SPT1_TX) +#define bfin_read_SPT1_TX() bfin_read16(SPT1_TX) +#define bfin_write_SPT1_TX(val) bfin_write16(SPT1_TX, val) +#define pSPT1_RX ((uint16_t volatile *)SPT1_RX) +#define bfin_read_SPT1_RX() bfin_read16(SPT1_RX) +#define bfin_write_SPT1_RX(val) bfin_write16(SPT1_RX, val) +#define pSPT1_TSCLKDIV ((uint16_t volatile *)SPT1_TSCLKDIV) +#define bfin_read_SPT1_TSCLKDIV() bfin_read16(SPT1_TSCLKDIV) +#define bfin_write_SPT1_TSCLKDIV(val) bfin_write16(SPT1_TSCLKDIV, val) +#define pSPT1_RSCLKDIV ((uint16_t volatile *)SPT1_RSCLKDIV) +#define bfin_read_SPT1_RSCLKDIV() bfin_read16(SPT1_RSCLKDIV) +#define bfin_write_SPT1_RSCLKDIV(val) bfin_write16(SPT1_RSCLKDIV, val) +#define pSPT1_TFSDIV ((uint16_t volatile *)SPT1_TFSDIV) +#define bfin_read_SPT1_TFSDIV() bfin_read16(SPT1_TFSDIV) +#define bfin_write_SPT1_TFSDIV(val) bfin_write16(SPT1_TFSDIV, val) +#define pSPT1_RFSDIV ((uint16_t volatile *)SPT1_RFSDIV) +#define bfin_read_SPT1_RFSDIV() bfin_read16(SPT1_RFSDIV) +#define bfin_write_SPT1_RFSDIV(val) bfin_write16(SPT1_RFSDIV, val) +#define pSPT1_STAT ((uint16_t volatile *)SPT1_STAT) +#define bfin_read_SPT1_STAT() bfin_read16(SPT1_STAT) +#define bfin_write_SPT1_STAT(val) bfin_write16(SPT1_STAT, val) +#define pSPT1_MTCS0 ((uint16_t volatile *)SPT1_MTCS0) +#define bfin_read_SPT1_MTCS0() bfin_read16(SPT1_MTCS0) +#define bfin_write_SPT1_MTCS0(val) bfin_write16(SPT1_MTCS0, val) +#define pSPT1_MTCS1 ((uint16_t volatile *)SPT1_MTCS1) +#define bfin_read_SPT1_MTCS1() bfin_read16(SPT1_MTCS1) +#define bfin_write_SPT1_MTCS1(val) bfin_write16(SPT1_MTCS1, val) +#define pSPT1_MTCS2 ((uint16_t volatile *)SPT1_MTCS2) +#define bfin_read_SPT1_MTCS2() bfin_read16(SPT1_MTCS2) +#define bfin_write_SPT1_MTCS2(val) bfin_write16(SPT1_MTCS2, val) +#define pSPT1_MTCS3 ((uint16_t volatile *)SPT1_MTCS3) +#define bfin_read_SPT1_MTCS3() bfin_read16(SPT1_MTCS3) +#define bfin_write_SPT1_MTCS3(val) bfin_write16(SPT1_MTCS3, val) +#define pSPT1_MTCS4 ((uint16_t volatile *)SPT1_MTCS4) +#define bfin_read_SPT1_MTCS4() bfin_read16(SPT1_MTCS4) +#define bfin_write_SPT1_MTCS4(val) bfin_write16(SPT1_MTCS4, val) +#define pSPT1_MTCS5 ((uint16_t volatile *)SPT1_MTCS5) +#define bfin_read_SPT1_MTCS5() bfin_read16(SPT1_MTCS5) +#define bfin_write_SPT1_MTCS5(val) bfin_write16(SPT1_MTCS5, val) +#define pSPT1_MTCS6 ((uint16_t volatile *)SPT1_MTCS6) +#define bfin_read_SPT1_MTCS6() bfin_read16(SPT1_MTCS6) +#define bfin_write_SPT1_MTCS6(val) bfin_write16(SPT1_MTCS6, val) +#define pSPT1_MTCS7 ((uint16_t volatile *)SPT1_MTCS7) +#define bfin_read_SPT1_MTCS7() bfin_read16(SPT1_MTCS7) +#define bfin_write_SPT1_MTCS7(val) bfin_write16(SPT1_MTCS7, val) +#define pSPT1_MRCS0 ((uint16_t volatile *)SPT1_MRCS0) +#define bfin_read_SPT1_MRCS0() bfin_read16(SPT1_MRCS0) +#define bfin_write_SPT1_MRCS0(val) bfin_write16(SPT1_MRCS0, val) +#define pSPT1_MRCS1 ((uint16_t volatile *)SPT1_MRCS1) +#define bfin_read_SPT1_MRCS1() bfin_read16(SPT1_MRCS1) +#define bfin_write_SPT1_MRCS1(val) bfin_write16(SPT1_MRCS1, val) +#define pSPT1_MRCS2 ((uint16_t volatile *)SPT1_MRCS2) +#define bfin_read_SPT1_MRCS2() bfin_read16(SPT1_MRCS2) +#define bfin_write_SPT1_MRCS2(val) bfin_write16(SPT1_MRCS2, val) +#define pSPT1_MRCS3 ((uint16_t volatile *)SPT1_MRCS3) +#define bfin_read_SPT1_MRCS3() bfin_read16(SPT1_MRCS3) +#define bfin_write_SPT1_MRCS3(val) bfin_write16(SPT1_MRCS3, val) +#define pSPT1_MRCS4 ((uint16_t volatile *)SPT1_MRCS4) +#define bfin_read_SPT1_MRCS4() bfin_read16(SPT1_MRCS4) +#define bfin_write_SPT1_MRCS4(val) bfin_write16(SPT1_MRCS4, val) +#define pSPT1_MRCS5 ((uint16_t volatile *)SPT1_MRCS5) +#define bfin_read_SPT1_MRCS5() bfin_read16(SPT1_MRCS5) +#define bfin_write_SPT1_MRCS5(val) bfin_write16(SPT1_MRCS5, val) +#define pSPT1_MRCS6 ((uint16_t volatile *)SPT1_MRCS6) +#define bfin_read_SPT1_MRCS6() bfin_read16(SPT1_MRCS6) +#define bfin_write_SPT1_MRCS6(val) bfin_write16(SPT1_MRCS6, val) +#define pSPT1_MRCS7 ((uint16_t volatile *)SPT1_MRCS7) +#define bfin_read_SPT1_MRCS7() bfin_read16(SPT1_MRCS7) +#define bfin_write_SPT1_MRCS7(val) bfin_write16(SPT1_MRCS7, val) +#define pSPT1_MCMC1 ((uint16_t volatile *)SPT1_MCMC1) +#define bfin_read_SPT1_MCMC1() bfin_read16(SPT1_MCMC1) +#define bfin_write_SPT1_MCMC1(val) bfin_write16(SPT1_MCMC1, val) +#define pSPT1_MCMC2 ((uint16_t volatile *)SPT1_MCMC2) +#define bfin_read_SPT1_MCMC2() bfin_read16(SPT1_MCMC2) +#define bfin_write_SPT1_MCMC2(val) bfin_write16(SPT1_MCMC2, val) +#define pSPT1_RX_CURR_PTR ((uint16_t volatile *)SPT1_RX_CURR_PTR) +#define bfin_read_SPT1_RX_CURR_PTR() bfin_read16(SPT1_RX_CURR_PTR) +#define bfin_write_SPT1_RX_CURR_PTR(val) bfin_write16(SPT1_RX_CURR_PTR, val) +#define pSPT1_RX_CONFIG_DMA ((uint16_t volatile *)SPT1_RX_CONFIG_DMA) +#define bfin_read_SPT1_RX_CONFIG_DMA() bfin_read16(SPT1_RX_CONFIG_DMA) +#define bfin_write_SPT1_RX_CONFIG_DMA(val) bfin_write16(SPT1_RX_CONFIG_DMA, val) +#define pSPT1_RX_START_PG ((uint16_t volatile *)SPT1_RX_START_PG) +#define bfin_read_SPT1_RX_START_PG() bfin_read16(SPT1_RX_START_PG) +#define bfin_write_SPT1_RX_START_PG(val) bfin_write16(SPT1_RX_START_PG, val) +#define pSPT1_RX_START_ADDR ((uint16_t volatile *)SPT1_RX_START_ADDR) +#define bfin_read_SPT1_RX_START_ADDR() bfin_read16(SPT1_RX_START_ADDR) +#define bfin_write_SPT1_RX_START_ADDR(val) bfin_write16(SPT1_RX_START_ADDR, val) +#define pSPT1_RX_COUNT ((uint16_t volatile *)SPT1_RX_COUNT) +#define bfin_read_SPT1_RX_COUNT() bfin_read16(SPT1_RX_COUNT) +#define bfin_write_SPT1_RX_COUNT(val) bfin_write16(SPT1_RX_COUNT, val) +#define pSPT1_RX_NEXT_DESCR ((uint16_t volatile *)SPT1_RX_NEXT_DESCR) +#define bfin_read_SPT1_RX_NEXT_DESCR() bfin_read16(SPT1_RX_NEXT_DESCR) +#define bfin_write_SPT1_RX_NEXT_DESCR(val) bfin_write16(SPT1_RX_NEXT_DESCR, val) +#define pSPT1_RX_DESCR_RDY ((uint16_t volatile *)SPT1_RX_DESCR_RDY) +#define bfin_read_SPT1_RX_DESCR_RDY() bfin_read16(SPT1_RX_DESCR_RDY) +#define bfin_write_SPT1_RX_DESCR_RDY(val) bfin_write16(SPT1_RX_DESCR_RDY, val) +#define pSPT1_RX_IRQSTAT ((uint16_t volatile *)SPT1_RX_IRQSTAT) +#define bfin_read_SPT1_RX_IRQSTAT() bfin_read16(SPT1_RX_IRQSTAT) +#define bfin_write_SPT1_RX_IRQSTAT(val) bfin_write16(SPT1_RX_IRQSTAT, val) +#define pSPT1_TX_CURR_PTR ((uint16_t volatile *)SPT1_TX_CURR_PTR) +#define bfin_read_SPT1_TX_CURR_PTR() bfin_read16(SPT1_TX_CURR_PTR) +#define bfin_write_SPT1_TX_CURR_PTR(val) bfin_write16(SPT1_TX_CURR_PTR, val) +#define pSPT1_TX_CONFIG_DMA ((uint16_t volatile *)SPT1_TX_CONFIG_DMA) +#define bfin_read_SPT1_TX_CONFIG_DMA() bfin_read16(SPT1_TX_CONFIG_DMA) +#define bfin_write_SPT1_TX_CONFIG_DMA(val) bfin_write16(SPT1_TX_CONFIG_DMA, val) +#define pSPT1_TX_START_PG ((uint16_t volatile *)SPT1_TX_START_PG) +#define bfin_read_SPT1_TX_START_PG() bfin_read16(SPT1_TX_START_PG) +#define bfin_write_SPT1_TX_START_PG(val) bfin_write16(SPT1_TX_START_PG, val) +#define pSPT1_TX_START_ADDR ((uint16_t volatile *)SPT1_TX_START_ADDR) +#define bfin_read_SPT1_TX_START_ADDR() bfin_read16(SPT1_TX_START_ADDR) +#define bfin_write_SPT1_TX_START_ADDR(val) bfin_write16(SPT1_TX_START_ADDR, val) +#define pSPT1_TX_COUNT ((uint16_t volatile *)SPT1_TX_COUNT) +#define bfin_read_SPT1_TX_COUNT() bfin_read16(SPT1_TX_COUNT) +#define bfin_write_SPT1_TX_COUNT(val) bfin_write16(SPT1_TX_COUNT, val) +#define pSPT1_TX_NEXT_DESCR ((uint16_t volatile *)SPT1_TX_NEXT_DESCR) +#define bfin_read_SPT1_TX_NEXT_DESCR() bfin_read16(SPT1_TX_NEXT_DESCR) +#define bfin_write_SPT1_TX_NEXT_DESCR(val) bfin_write16(SPT1_TX_NEXT_DESCR, val) +#define pSPT1_TX_DESCR_RDY ((uint16_t volatile *)SPT1_TX_DESCR_RDY) +#define bfin_read_SPT1_TX_DESCR_RDY() bfin_read16(SPT1_TX_DESCR_RDY) +#define bfin_write_SPT1_TX_DESCR_RDY(val) bfin_write16(SPT1_TX_DESCR_RDY, val) +#define pSPT1_TX_IRQSTAT ((uint16_t volatile *)SPT1_TX_IRQSTAT) +#define bfin_read_SPT1_TX_IRQSTAT() bfin_read16(SPT1_TX_IRQSTAT) +#define bfin_write_SPT1_TX_IRQSTAT(val) bfin_write16(SPT1_TX_IRQSTAT, val) +#define pSPI0_SPICTL ((uint16_t volatile *)SPI0_SPICTL) +#define bfin_read_SPI0_SPICTL() bfin_read16(SPI0_SPICTL) +#define bfin_write_SPI0_SPICTL(val) bfin_write16(SPI0_SPICTL, val) +#define pSPI0_SPIFLG ((uint16_t volatile *)SPI0_SPIFLG) +#define bfin_read_SPI0_SPIFLG() bfin_read16(SPI0_SPIFLG) +#define bfin_write_SPI0_SPIFLG(val) bfin_write16(SPI0_SPIFLG, val) +#define pSPI0_SPIST ((uint16_t volatile *)SPI0_SPIST) +#define bfin_read_SPI0_SPIST() bfin_read16(SPI0_SPIST) +#define bfin_write_SPI0_SPIST(val) bfin_write16(SPI0_SPIST, val) +#define pSPI0_TDBR ((uint16_t volatile *)SPI0_TDBR) +#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR) +#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val) +#define pSPI0_RDBR ((uint16_t volatile *)SPI0_RDBR) +#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR) +#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val) +#define pSPI0_SPIBAUD ((uint16_t volatile *)SPI0_SPIBAUD) +#define bfin_read_SPI0_SPIBAUD() bfin_read16(SPI0_SPIBAUD) +#define bfin_write_SPI0_SPIBAUD(val) bfin_write16(SPI0_SPIBAUD, val) +#define pSPI0_DMACURR ((uint16_t volatile *)SPI0_DMACURR) +#define bfin_read_SPI0_DMACURR() bfin_read16(SPI0_DMACURR) +#define bfin_write_SPI0_DMACURR(val) bfin_write16(SPI0_DMACURR, val) +#define pSPI0_DMACONF ((uint16_t volatile *)SPI0_DMACONF) +#define bfin_read_SPI0_DMACONF() bfin_read16(SPI0_DMACONF) +#define bfin_write_SPI0_DMACONF(val) bfin_write16(SPI0_DMACONF, val) +#define pSPI0_DMASPAGE ((uint16_t volatile *)SPI0_DMASPAGE) +#define bfin_read_SPI0_DMASPAGE() bfin_read16(SPI0_DMASPAGE) +#define bfin_write_SPI0_DMASPAGE(val) bfin_write16(SPI0_DMASPAGE, val) +#define pSPI0_DMASADD ((uint16_t volatile *)SPI0_DMASADD) +#define bfin_read_SPI0_DMASADD() bfin_read16(SPI0_DMASADD) +#define bfin_write_SPI0_DMASADD(val) bfin_write16(SPI0_DMASADD, val) +#define pSPI0_DMACNT ((uint16_t volatile *)SPI0_DMACNT) +#define bfin_read_SPI0_DMACNT() bfin_read16(SPI0_DMACNT) +#define bfin_write_SPI0_DMACNT(val) bfin_write16(SPI0_DMACNT, val) +#define pSPI0_DMANEXT ((uint16_t volatile *)SPI0_DMANEXT) +#define bfin_read_SPI0_DMANEXT() bfin_read16(SPI0_DMANEXT) +#define bfin_write_SPI0_DMANEXT(val) bfin_write16(SPI0_DMANEXT, val) +#define pSPI0_DMADRDY ((uint16_t volatile *)SPI0_DMADRDY) +#define bfin_read_SPI0_DMADRDY() bfin_read16(SPI0_DMADRDY) +#define bfin_write_SPI0_DMADRDY(val) bfin_write16(SPI0_DMADRDY, val) +#define pSPI0_DMAIRQ ((uint16_t volatile *)SPI0_DMAIRQ) +#define bfin_read_SPI0_DMAIRQ() bfin_read16(SPI0_DMAIRQ) +#define bfin_write_SPI0_DMAIRQ(val) bfin_write16(SPI0_DMAIRQ, val) +#define pSPI1_SPICTL ((uint16_t volatile *)SPI1_SPICTL) +#define bfin_read_SPI1_SPICTL() bfin_read16(SPI1_SPICTL) +#define bfin_write_SPI1_SPICTL(val) bfin_write16(SPI1_SPICTL, val) +#define pSPI1_SPIFLG ((uint16_t volatile *)SPI1_SPIFLG) +#define bfin_read_SPI1_SPIFLG() bfin_read16(SPI1_SPIFLG) +#define bfin_write_SPI1_SPIFLG(val) bfin_write16(SPI1_SPIFLG, val) +#define pSPI1_SPIST ((uint16_t volatile *)SPI1_SPIST) +#define bfin_read_SPI1_SPIST() bfin_read16(SPI1_SPIST) +#define bfin_write_SPI1_SPIST(val) bfin_write16(SPI1_SPIST, val) +#define pSPI1_TDBR ((uint16_t volatile *)SPI1_TDBR) +#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR) +#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val) +#define pSPI1_RDBR ((uint16_t volatile *)SPI1_RDBR) +#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR) +#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val) +#define pSPI1_SPIBAUD ((uint16_t volatile *)SPI1_SPIBAUD) +#define bfin_read_SPI1_SPIBAUD() bfin_read16(SPI1_SPIBAUD) +#define bfin_write_SPI1_SPIBAUD(val) bfin_write16(SPI1_SPIBAUD, val) +#define pSPI1_DMACURR ((uint16_t volatile *)SPI1_DMACURR) +#define bfin_read_SPI1_DMACURR() bfin_read16(SPI1_DMACURR) +#define bfin_write_SPI1_DMACURR(val) bfin_write16(SPI1_DMACURR, val) +#define pSPI1_DMACONF ((uint16_t volatile *)SPI1_DMACONF) +#define bfin_read_SPI1_DMACONF() bfin_read16(SPI1_DMACONF) +#define bfin_write_SPI1_DMACONF(val) bfin_write16(SPI1_DMACONF, val) +#define pSPI1_DMASPAGE ((uint16_t volatile *)SPI1_DMASPAGE) +#define bfin_read_SPI1_DMASPAGE() bfin_read16(SPI1_DMASPAGE) +#define bfin_write_SPI1_DMASPAGE(val) bfin_write16(SPI1_DMASPAGE, val) +#define pSPI1_DMASADD ((uint16_t volatile *)SPI1_DMASADD) +#define bfin_read_SPI1_DMASADD() bfin_read16(SPI1_DMASADD) +#define bfin_write_SPI1_DMASADD(val) bfin_write16(SPI1_DMASADD, val) +#define pSPI1_DMACNT ((uint16_t volatile *)SPI1_DMACNT) +#define bfin_read_SPI1_DMACNT() bfin_read16(SPI1_DMACNT) +#define bfin_write_SPI1_DMACNT(val) bfin_write16(SPI1_DMACNT, val) +#define pSPI1_DMANEXT ((uint16_t volatile *)SPI1_DMANEXT) +#define bfin_read_SPI1_DMANEXT() bfin_read16(SPI1_DMANEXT) +#define bfin_write_SPI1_DMANEXT(val) bfin_write16(SPI1_DMANEXT, val) +#define pSPI1_DMADRDY ((uint16_t volatile *)SPI1_DMADRDY) +#define bfin_read_SPI1_DMADRDY() bfin_read16(SPI1_DMADRDY) +#define bfin_write_SPI1_DMADRDY(val) bfin_write16(SPI1_DMADRDY, val) +#define pSPI1_DMAIRQ ((uint16_t volatile *)SPI1_DMAIRQ) +#define bfin_read_SPI1_DMAIRQ() bfin_read16(SPI1_DMAIRQ) +#define bfin_write_SPI1_DMAIRQ(val) bfin_write16(SPI1_DMAIRQ, val) +#define pUSBD_ID ((uint16_t volatile *)USBD_ID) +#define bfin_read_USBD_ID() bfin_read16(USBD_ID) +#define bfin_write_USBD_ID(val) bfin_write16(USBD_ID, val) +#define pUSBD_FRM ((uint16_t volatile *)USBD_FRM) +#define bfin_read_USBD_FRM() bfin_read16(USBD_FRM) +#define bfin_write_USBD_FRM(val) bfin_write16(USBD_FRM, val) +#define pUSBD_FRMAT ((uint16_t volatile *)USBD_FRMAT) +#define bfin_read_USBD_FRMAT() bfin_read16(USBD_FRMAT) +#define bfin_write_USBD_FRMAT(val) bfin_write16(USBD_FRMAT, val) +#define pUSBD_EPBUF ((uint16_t volatile *)USBD_EPBUF) +#define bfin_read_USBD_EPBUF() bfin_read16(USBD_EPBUF) +#define bfin_write_USBD_EPBUF(val) bfin_write16(USBD_EPBUF, val) +#define pUSBD_STAT ((uint16_t volatile *)USBD_STAT) +#define bfin_read_USBD_STAT() bfin_read16(USBD_STAT) +#define bfin_write_USBD_STAT(val) bfin_write16(USBD_STAT, val) +#define pUSBD_CTRL ((uint16_t volatile *)USBD_CTRL) +#define bfin_read_USBD_CTRL() bfin_read16(USBD_CTRL) +#define bfin_write_USBD_CTRL(val) bfin_write16(USBD_CTRL, val) +#define pUSBD_GINTR ((uint16_t volatile *)USBD_GINTR) +#define bfin_read_USBD_GINTR() bfin_read16(USBD_GINTR) +#define bfin_write_USBD_GINTR(val) bfin_write16(USBD_GINTR, val) +#define pUSBD_GMASK ((uint16_t volatile *)USBD_GMASK) +#define bfin_read_USBD_GMASK() bfin_read16(USBD_GMASK) +#define bfin_write_USBD_GMASK(val) bfin_write16(USBD_GMASK, val) +#define pUSBD_DMACFG ((uint16_t volatile *)USBD_DMACFG) +#define bfin_read_USBD_DMACFG() bfin_read16(USBD_DMACFG) +#define bfin_write_USBD_DMACFG(val) bfin_write16(USBD_DMACFG, val) +#define pUSBD_DMABL ((uint16_t volatile *)USBD_DMABL) +#define bfin_read_USBD_DMABL() bfin_read16(USBD_DMABL) +#define bfin_write_USBD_DMABL(val) bfin_write16(USBD_DMABL, val) +#define pUSBD_DMABH ((uint16_t volatile *)USBD_DMABH) +#define bfin_read_USBD_DMABH() bfin_read16(USBD_DMABH) +#define bfin_write_USBD_DMABH(val) bfin_write16(USBD_DMABH, val) +#define pUSBD_DMACT ((uint16_t volatile *)USBD_DMACT) +#define bfin_read_USBD_DMACT() bfin_read16(USBD_DMACT) +#define bfin_write_USBD_DMACT(val) bfin_write16(USBD_DMACT, val) +#define pUSBD_DMAIRQ ((uint16_t volatile *)USBD_DMAIRQ) +#define bfin_read_USBD_DMAIRQ() bfin_read16(USBD_DMAIRQ) +#define bfin_write_USBD_DMAIRQ(val) bfin_write16(USBD_DMAIRQ, val) +#define pUSBD_INTR0 ((uint16_t volatile *)USBD_INTR0) +#define bfin_read_USBD_INTR0() bfin_read16(USBD_INTR0) +#define bfin_write_USBD_INTR0(val) bfin_write16(USBD_INTR0, val) +#define pUSBD_MASK0 ((uint16_t volatile *)USBD_MASK0) +#define bfin_read_USBD_MASK0() bfin_read16(USBD_MASK0) +#define bfin_write_USBD_MASK0(val) bfin_write16(USBD_MASK0, val) +#define pUSBD_EPCFG0 ((uint16_t volatile *)USBD_EPCFG0) +#define bfin_read_USBD_EPCFG0() bfin_read16(USBD_EPCFG0) +#define bfin_write_USBD_EPCFG0(val) bfin_write16(USBD_EPCFG0, val) +#define pUSBD_EPADR0 ((uint16_t volatile *)USBD_EPADR0) +#define bfin_read_USBD_EPADR0() bfin_read16(USBD_EPADR0) +#define bfin_write_USBD_EPADR0(val) bfin_write16(USBD_EPADR0, val) +#define pUSBD_EPLEN0 ((uint16_t volatile *)USBD_EPLEN0) +#define bfin_read_USBD_EPLEN0() bfin_read16(USBD_EPLEN0) +#define bfin_write_USBD_EPLEN0(val) bfin_write16(USBD_EPLEN0, val) +#define pUSBD_INTR1 ((uint16_t volatile *)USBD_INTR1) +#define bfin_read_USBD_INTR1() bfin_read16(USBD_INTR1) +#define bfin_write_USBD_INTR1(val) bfin_write16(USBD_INTR1, val) +#define pUSBD_MASK1 ((uint16_t volatile *)USBD_MASK1) +#define bfin_read_USBD_MASK1() bfin_read16(USBD_MASK1) +#define bfin_write_USBD_MASK1(val) bfin_write16(USBD_MASK1, val) +#define pUSBD_EPCFG1 ((uint16_t volatile *)USBD_EPCFG1) +#define bfin_read_USBD_EPCFG1() bfin_read16(USBD_EPCFG1) +#define bfin_write_USBD_EPCFG1(val) bfin_write16(USBD_EPCFG1, val) +#define pUSBD_EPADR1 ((uint16_t volatile *)USBD_EPADR1) +#define bfin_read_USBD_EPADR1() bfin_read16(USBD_EPADR1) +#define bfin_write_USBD_EPADR1(val) bfin_write16(USBD_EPADR1, val) +#define pUSBD_EPLEN1 ((uint16_t volatile *)USBD_EPLEN1) +#define bfin_read_USBD_EPLEN1() bfin_read16(USBD_EPLEN1) +#define bfin_write_USBD_EPLEN1(val) bfin_write16(USBD_EPLEN1, val) +#define pUSBD_INTR2 ((uint16_t volatile *)USBD_INTR2) +#define bfin_read_USBD_INTR2() bfin_read16(USBD_INTR2) +#define bfin_write_USBD_INTR2(val) bfin_write16(USBD_INTR2, val) +#define pUSBD_MASK2 ((uint16_t volatile *)USBD_MASK2) +#define bfin_read_USBD_MASK2() bfin_read16(USBD_MASK2) +#define bfin_write_USBD_MASK2(val) bfin_write16(USBD_MASK2, val) +#define pUSBD_EPCFG2 ((uint16_t volatile *)USBD_EPCFG2) +#define bfin_read_USBD_EPCFG2() bfin_read16(USBD_EPCFG2) +#define bfin_write_USBD_EPCFG2(val) bfin_write16(USBD_EPCFG2, val) +#define pUSBD_EPADR2 ((uint16_t volatile *)USBD_EPADR2) +#define bfin_read_USBD_EPADR2() bfin_read16(USBD_EPADR2) +#define bfin_write_USBD_EPADR2(val) bfin_write16(USBD_EPADR2, val) +#define pUSBD_EPLEN2 ((uint16_t volatile *)USBD_EPLEN2) +#define bfin_read_USBD_EPLEN2() bfin_read16(USBD_EPLEN2) +#define bfin_write_USBD_EPLEN2(val) bfin_write16(USBD_EPLEN2, val) +#define pUSBD_INTR3 ((uint16_t volatile *)USBD_INTR3) +#define bfin_read_USBD_INTR3() bfin_read16(USBD_INTR3) +#define bfin_write_USBD_INTR3(val) bfin_write16(USBD_INTR3, val) +#define pUSBD_MASK3 ((uint16_t volatile *)USBD_MASK3) +#define bfin_read_USBD_MASK3() bfin_read16(USBD_MASK3) +#define bfin_write_USBD_MASK3(val) bfin_write16(USBD_MASK3, val) +#define pUSBD_EPCFG3 ((uint16_t volatile *)USBD_EPCFG3) +#define bfin_read_USBD_EPCFG3() bfin_read16(USBD_EPCFG3) +#define bfin_write_USBD_EPCFG3(val) bfin_write16(USBD_EPCFG3, val) +#define pUSBD_EPADR3 ((uint16_t volatile *)USBD_EPADR3) +#define bfin_read_USBD_EPADR3() bfin_read16(USBD_EPADR3) +#define bfin_write_USBD_EPADR3(val) bfin_write16(USBD_EPADR3, val) +#define pUSBD_EPLEN3 ((uint16_t volatile *)USBD_EPLEN3) +#define bfin_read_USBD_EPLEN3() bfin_read16(USBD_EPLEN3) +#define bfin_write_USBD_EPLEN3(val) bfin_write16(USBD_EPLEN3, val) +#define pUSBD_INTR4 ((uint16_t volatile *)USBD_INTR4) +#define bfin_read_USBD_INTR4() bfin_read16(USBD_INTR4) +#define bfin_write_USBD_INTR4(val) bfin_write16(USBD_INTR4, val) +#define pUSBD_MASK4 ((uint16_t volatile *)USBD_MASK4) +#define bfin_read_USBD_MASK4() bfin_read16(USBD_MASK4) +#define bfin_write_USBD_MASK4(val) bfin_write16(USBD_MASK4, val) +#define pUSBD_EPCFG4 ((uint16_t volatile *)USBD_EPCFG4) +#define bfin_read_USBD_EPCFG4() bfin_read16(USBD_EPCFG4) +#define bfin_write_USBD_EPCFG4(val) bfin_write16(USBD_EPCFG4, val) +#define pUSBD_EPADR4 ((uint16_t volatile *)USBD_EPADR4) +#define bfin_read_USBD_EPADR4() bfin_read16(USBD_EPADR4) +#define bfin_write_USBD_EPADR4(val) bfin_write16(USBD_EPADR4, val) +#define pUSBD_EPLEN4 ((uint16_t volatile *)USBD_EPLEN4) +#define bfin_read_USBD_EPLEN4() bfin_read16(USBD_EPLEN4) +#define bfin_write_USBD_EPLEN4(val) bfin_write16(USBD_EPLEN4, val) +#define pUSBD_INTR5 ((uint16_t volatile *)USBD_INTR5) +#define bfin_read_USBD_INTR5() bfin_read16(USBD_INTR5) +#define bfin_write_USBD_INTR5(val) bfin_write16(USBD_INTR5, val) +#define pUSBD_MASK5 ((uint16_t volatile *)USBD_MASK5) +#define bfin_read_USBD_MASK5() bfin_read16(USBD_MASK5) +#define bfin_write_USBD_MASK5(val) bfin_write16(USBD_MASK5, val) +#define pUSBD_EPCFG5 ((uint16_t volatile *)USBD_EPCFG5) +#define bfin_read_USBD_EPCFG5() bfin_read16(USBD_EPCFG5) +#define bfin_write_USBD_EPCFG5(val) bfin_write16(USBD_EPCFG5, val) +#define pUSBD_EPADR5 ((uint16_t volatile *)USBD_EPADR5) +#define bfin_read_USBD_EPADR5() bfin_read16(USBD_EPADR5) +#define bfin_write_USBD_EPADR5(val) bfin_write16(USBD_EPADR5, val) +#define pUSBD_EPLEN5 ((uint16_t volatile *)USBD_EPLEN5) +#define bfin_read_USBD_EPLEN5() bfin_read16(USBD_EPLEN5) +#define bfin_write_USBD_EPLEN5(val) bfin_write16(USBD_EPLEN5, val) +#define pUSBD_INTR6 ((uint16_t volatile *)USBD_INTR6) +#define bfin_read_USBD_INTR6() bfin_read16(USBD_INTR6) +#define bfin_write_USBD_INTR6(val) bfin_write16(USBD_INTR6, val) +#define pUSBD_MASK6 ((uint16_t volatile *)USBD_MASK6) +#define bfin_read_USBD_MASK6() bfin_read16(USBD_MASK6) +#define bfin_write_USBD_MASK6(val) bfin_write16(USBD_MASK6, val) +#define pUSBD_EPCFG6 ((uint16_t volatile *)USBD_EPCFG6) +#define bfin_read_USBD_EPCFG6() bfin_read16(USBD_EPCFG6) +#define bfin_write_USBD_EPCFG6(val) bfin_write16(USBD_EPCFG6, val) +#define pUSBD_EPADR6 ((uint16_t volatile *)USBD_EPADR6) +#define bfin_read_USBD_EPADR6() bfin_read16(USBD_EPADR6) +#define bfin_write_USBD_EPADR6(val) bfin_write16(USBD_EPADR6, val) +#define pUSBD_EPLEN6 ((uint16_t volatile *)USBD_EPLEN6) +#define bfin_read_USBD_EPLEN6() bfin_read16(USBD_EPLEN6) +#define bfin_write_USBD_EPLEN6(val) bfin_write16(USBD_EPLEN6, val) +#define pUSBD_INTR7 ((uint16_t volatile *)USBD_INTR7) +#define bfin_read_USBD_INTR7() bfin_read16(USBD_INTR7) +#define bfin_write_USBD_INTR7(val) bfin_write16(USBD_INTR7, val) +#define pUSBD_MASK7 ((uint16_t volatile *)USBD_MASK7) +#define bfin_read_USBD_MASK7() bfin_read16(USBD_MASK7) +#define bfin_write_USBD_MASK7(val) bfin_write16(USBD_MASK7, val) +#define pUSBD_EPCFG7 ((uint16_t volatile *)USBD_EPCFG7) +#define bfin_read_USBD_EPCFG7() bfin_read16(USBD_EPCFG7) +#define bfin_write_USBD_EPCFG7(val) bfin_write16(USBD_EPCFG7, val) +#define pUSBD_EPADR7 ((uint16_t volatile *)USBD_EPADR7) +#define bfin_read_USBD_EPADR7() bfin_read16(USBD_EPADR7) +#define bfin_write_USBD_EPADR7(val) bfin_write16(USBD_EPADR7, val) +#define pUSBD_EPLEN7 ((uint16_t volatile *)USBD_EPLEN7) +#define bfin_read_USBD_EPLEN7() bfin_read16(USBD_EPLEN7) +#define bfin_write_USBD_EPLEN7(val) bfin_write16(USBD_EPLEN7, val) +#define pGPIO_DIR ((uint16_t volatile *)GPIO_DIR) +#define bfin_read_GPIO_DIR() bfin_read16(GPIO_DIR) +#define bfin_write_GPIO_DIR(val) bfin_write16(GPIO_DIR, val) +#define pGPIO_FLAG_CLR ((uint16_t volatile *)GPIO_FLAG_CLR) +#define bfin_read_GPIO_FLAG_CLR() bfin_read16(GPIO_FLAG_CLR) +#define bfin_write_GPIO_FLAG_CLR(val) bfin_write16(GPIO_FLAG_CLR, val) +#define pGPIO_FLAG_SET ((uint16_t volatile *)GPIO_FLAG_SET) +#define bfin_read_GPIO_FLAG_SET() bfin_read16(GPIO_FLAG_SET) +#define bfin_write_GPIO_FLAG_SET(val) bfin_write16(GPIO_FLAG_SET, val) +#define pGPIO_MASKA_CLR ((uint16_t volatile *)GPIO_MASKA_CLR) +#define bfin_read_GPIO_MASKA_CLR() bfin_read16(GPIO_MASKA_CLR) +#define bfin_write_GPIO_MASKA_CLR(val) bfin_write16(GPIO_MASKA_CLR, val) +#define pGPIO_MASKA_SET ((uint16_t volatile *)GPIO_MASKA_SET) +#define bfin_read_GPIO_MASKA_SET() bfin_read16(GPIO_MASKA_SET) +#define bfin_write_GPIO_MASKA_SET(val) bfin_write16(GPIO_MASKA_SET, val) +#define pGPIO_MASKB_CLR ((uint16_t volatile *)GPIO_MASKB_CLR) +#define bfin_read_GPIO_MASKB_CLR() bfin_read16(GPIO_MASKB_CLR) +#define bfin_write_GPIO_MASKB_CLR(val) bfin_write16(GPIO_MASKB_CLR, val) +#define pGPIO_MASKB_SET ((uint16_t volatile *)GPIO_MASKB_SET) +#define bfin_read_GPIO_MASKB_SET() bfin_read16(GPIO_MASKB_SET) +#define bfin_write_GPIO_MASKB_SET(val) bfin_write16(GPIO_MASKB_SET, val) +#define pGPIO_POLAR ((uint16_t volatile *)GPIO_POLAR) +#define bfin_read_GPIO_POLAR() bfin_read16(GPIO_POLAR) +#define bfin_write_GPIO_POLAR(val) bfin_write16(GPIO_POLAR, val) +#define pGPIO_EDGE ((uint16_t volatile *)GPIO_EDGE) +#define bfin_read_GPIO_EDGE() bfin_read16(GPIO_EDGE) +#define bfin_write_GPIO_EDGE(val) bfin_write16(GPIO_EDGE, val) +#define pGPIO_BOTH ((uint16_t volatile *)GPIO_BOTH) +#define bfin_read_GPIO_BOTH() bfin_read16(GPIO_BOTH) +#define bfin_write_GPIO_BOTH(val) bfin_write16(GPIO_BOTH, val) +#define pPCI_CTL ((uint32_t volatile *)PCI_CTL) +#define bfin_read_PCI_CTL() bfin_read32(PCI_CTL) +#define bfin_write_PCI_CTL(val) bfin_write32(PCI_CTL, val) +#define pPCI_STAT ((uint32_t volatile *)PCI_STAT) +#define bfin_read_PCI_STAT() bfin_read32(PCI_STAT) +#define bfin_write_PCI_STAT(val) bfin_write32(PCI_STAT, val) +#define pPCI_ICTL ((uint32_t volatile *)PCI_ICTL) +#define bfin_read_PCI_ICTL() bfin_read32(PCI_ICTL) +#define bfin_write_PCI_ICTL(val) bfin_write32(PCI_ICTL, val) +#define pPCI_MBAP ((uint32_t volatile *)PCI_MBAP) +#define bfin_read_PCI_MBAP() bfin_read32(PCI_MBAP) +#define bfin_write_PCI_MBAP(val) bfin_write32(PCI_MBAP, val) +#define pPCI_IBAP ((uint32_t volatile *)PCI_IBAP) +#define bfin_read_PCI_IBAP() bfin_read32(PCI_IBAP) +#define bfin_write_PCI_IBAP(val) bfin_write32(PCI_IBAP, val) +#define pPCI_CBAP ((uint32_t volatile *)PCI_CBAP) +#define bfin_read_PCI_CBAP() bfin_read32(PCI_CBAP) +#define bfin_write_PCI_CBAP(val) bfin_write32(PCI_CBAP, val) +#define pPCI_TMBAP ((uint32_t volatile *)PCI_TMBAP) +#define bfin_read_PCI_TMBAP() bfin_read32(PCI_TMBAP) +#define bfin_write_PCI_TMBAP(val) bfin_write32(PCI_TMBAP, val) +#define pPCI_TIBAP ((uint32_t volatile *)PCI_TIBAP) +#define bfin_read_PCI_TIBAP() bfin_read32(PCI_TIBAP) +#define bfin_write_PCI_TIBAP(val) bfin_write32(PCI_TIBAP, val) +#define pPCI_DMBARM ((uint32_t volatile *)PCI_DMBARM) +#define bfin_read_PCI_DMBARM() bfin_read32(PCI_DMBARM) +#define bfin_write_PCI_DMBARM(val) bfin_write32(PCI_DMBARM, val) +#define pPCI_DIBARM ((uint32_t volatile *)PCI_DIBARM) +#define bfin_read_PCI_DIBARM() bfin_read32(PCI_DIBARM) +#define bfin_write_PCI_DIBARM(val) bfin_write32(PCI_DIBARM, val) +#define pPCI_CFG_DIC ((uint32_t volatile *)PCI_CFG_DIC) +#define bfin_read_PCI_CFG_DIC() bfin_read32(PCI_CFG_DIC) +#define bfin_write_PCI_CFG_DIC(val) bfin_write32(PCI_CFG_DIC, val) +#define pPCI_CFG_VIC ((uint32_t volatile *)PCI_CFG_VIC) +#define bfin_read_PCI_CFG_VIC() bfin_read32(PCI_CFG_VIC) +#define bfin_write_PCI_CFG_VIC(val) bfin_write32(PCI_CFG_VIC, val) +#define pPCI_CFG_STAT ((uint32_t volatile *)PCI_CFG_STAT) +#define bfin_read_PCI_CFG_STAT() bfin_read32(PCI_CFG_STAT) +#define bfin_write_PCI_CFG_STAT(val) bfin_write32(PCI_CFG_STAT, val) +#define pPCI_CFG_CMD ((uint32_t volatile *)PCI_CFG_CMD) +#define bfin_read_PCI_CFG_CMD() bfin_read32(PCI_CFG_CMD) +#define bfin_write_PCI_CFG_CMD(val) bfin_write32(PCI_CFG_CMD, val) +#define pPCI_CFG_CC ((uint32_t volatile *)PCI_CFG_CC) +#define bfin_read_PCI_CFG_CC() bfin_read32(PCI_CFG_CC) +#define bfin_write_PCI_CFG_CC(val) bfin_write32(PCI_CFG_CC, val) +#define pPCI_CFG_RID ((uint32_t volatile *)PCI_CFG_RID) +#define bfin_read_PCI_CFG_RID() bfin_read32(PCI_CFG_RID) +#define bfin_write_PCI_CFG_RID(val) bfin_write32(PCI_CFG_RID, val) +#define pPCI_CFG_BIST ((uint32_t volatile *)PCI_CFG_BIST) +#define bfin_read_PCI_CFG_BIST() bfin_read32(PCI_CFG_BIST) +#define bfin_write_PCI_CFG_BIST(val) bfin_write32(PCI_CFG_BIST, val) +#define pPCI_CFG_HT ((uint32_t volatile *)PCI_CFG_HT) +#define bfin_read_PCI_CFG_HT() bfin_read32(PCI_CFG_HT) +#define bfin_write_PCI_CFG_HT(val) bfin_write32(PCI_CFG_HT, val) +#define pPCI_CFG_MLT ((uint32_t volatile *)PCI_CFG_MLT) +#define bfin_read_PCI_CFG_MLT() bfin_read32(PCI_CFG_MLT) +#define bfin_write_PCI_CFG_MLT(val) bfin_write32(PCI_CFG_MLT, val) +#define pPCI_CFG_CLS ((uint32_t volatile *)PCI_CFG_CLS) +#define bfin_read_PCI_CFG_CLS() bfin_read32(PCI_CFG_CLS) +#define bfin_write_PCI_CFG_CLS(val) bfin_write32(PCI_CFG_CLS, val) +#define pPCI_CFG_MBAR ((uint32_t volatile *)PCI_CFG_MBAR) +#define bfin_read_PCI_CFG_MBAR() bfin_read32(PCI_CFG_MBAR) +#define bfin_write_PCI_CFG_MBAR(val) bfin_write32(PCI_CFG_MBAR, val) +#define pPCI_CFG_IBAR ((uint32_t volatile *)PCI_CFG_IBAR) +#define bfin_read_PCI_CFG_IBAR() bfin_read32(PCI_CFG_IBAR) +#define bfin_write_PCI_CFG_IBAR(val) bfin_write32(PCI_CFG_IBAR, val) +#define pPCI_CFG_SID ((uint32_t volatile *)PCI_CFG_SID) +#define bfin_read_PCI_CFG_SID() bfin_read32(PCI_CFG_SID) +#define bfin_write_PCI_CFG_SID(val) bfin_write32(PCI_CFG_SID, val) +#define pPCI_CFG_SVID ((uint32_t volatile *)PCI_CFG_SVID) +#define bfin_read_PCI_CFG_SVID() bfin_read32(PCI_CFG_SVID) +#define bfin_write_PCI_CFG_SVID(val) bfin_write32(PCI_CFG_SVID, val) +#define pPCI_CFG_MAXL ((uint32_t volatile *)PCI_CFG_MAXL) +#define bfin_read_PCI_CFG_MAXL() bfin_read32(PCI_CFG_MAXL) +#define bfin_write_PCI_CFG_MAXL(val) bfin_write32(PCI_CFG_MAXL, val) +#define pPCI_CFG_MING ((uint32_t volatile *)PCI_CFG_MING) +#define bfin_read_PCI_CFG_MING() bfin_read32(PCI_CFG_MING) +#define bfin_write_PCI_CFG_MING(val) bfin_write32(PCI_CFG_MING, val) +#define pPCI_CFG_IP ((uint32_t volatile *)PCI_CFG_IP) +#define bfin_read_PCI_CFG_IP() bfin_read32(PCI_CFG_IP) +#define bfin_write_PCI_CFG_IP(val) bfin_write32(PCI_CFG_IP, val) +#define pPCI_CFG_IL ((uint32_t volatile *)PCI_CFG_IL) +#define bfin_read_PCI_CFG_IL() bfin_read32(PCI_CFG_IL) +#define bfin_write_PCI_CFG_IL(val) bfin_write32(PCI_CFG_IL, val) +#define pPCI_HMCTL ((uint32_t volatile *)PCI_HMCTL) +#define bfin_read_PCI_HMCTL() bfin_read32(PCI_HMCTL) +#define bfin_write_PCI_HMCTL(val) bfin_write32(PCI_HMCTL, val) +#define pRTCSTAT ((uint32_t volatile *)RTCSTAT) +#define bfin_read_RTCSTAT() bfin_read32(RTCSTAT) +#define bfin_write_RTCSTAT(val) bfin_write32(RTCSTAT, val) +#define pRTCICTL ((uint16_t volatile *)RTCICTL) +#define bfin_read_RTCICTL() bfin_read16(RTCICTL) +#define bfin_write_RTCICTL(val) bfin_write16(RTCICTL, val) +#define pRTCISTAT ((uint16_t volatile *)RTCISTAT) +#define bfin_read_RTCISTAT() bfin_read16(RTCISTAT) +#define bfin_write_RTCISTAT(val) bfin_write16(RTCISTAT, val) +#define pRTCSWCNT ((uint16_t volatile *)RTCSWCNT) +#define bfin_read_RTCSWCNT() bfin_read16(RTCSWCNT) +#define bfin_write_RTCSWCNT(val) bfin_write16(RTCSWCNT, val) +#define pRTCALARM ((uint32_t volatile *)RTCALARM) +#define bfin_read_RTCALARM() bfin_read32(RTCALARM) +#define bfin_write_RTCALARM(val) bfin_write32(RTCALARM, val) +#define pRTCFAST ((uint16_t volatile *)RTCFAST) +#define bfin_read_RTCFAST() bfin_read16(RTCFAST) +#define bfin_write_RTCFAST(val) bfin_write16(RTCFAST, val) +#define pCurrent_desc_Wr ((uint16_t volatile *)Current_desc_Wr) +#define bfin_read_Current_desc_Wr() bfin_read16(Current_desc_Wr) +#define bfin_write_Current_desc_Wr(val) bfin_write16(Current_desc_Wr, val) +#define pConfig_Wr ((uint16_t volatile *)Config_Wr) +#define bfin_read_Config_Wr() bfin_read16(Config_Wr) +#define bfin_write_Config_Wr(val) bfin_write16(Config_Wr, val) +#define pStart_page_Wr ((uint16_t volatile *)Start_page_Wr) +#define bfin_read_Start_page_Wr() bfin_read16(Start_page_Wr) +#define bfin_write_Start_page_Wr(val) bfin_write16(Start_page_Wr, val) +#define pStart_addr_Wr ((uint16_t volatile *)Start_addr_Wr) +#define bfin_read_Start_addr_Wr() bfin_read16(Start_addr_Wr) +#define bfin_write_Start_addr_Wr(val) bfin_write16(Start_addr_Wr, val) +#define pWord_count_Wr ((uint16_t volatile *)Word_count_Wr) +#define bfin_read_Word_count_Wr() bfin_read16(Word_count_Wr) +#define bfin_write_Word_count_Wr(val) bfin_write16(Word_count_Wr, val) +#define pNext_desc_Wr ((uint16_t volatile *)Next_desc_Wr) +#define bfin_read_Next_desc_Wr() bfin_read16(Next_desc_Wr) +#define bfin_write_Next_desc_Wr(val) bfin_write16(Next_desc_Wr, val) +#define pDesc_ready_Wr ((uint16_t volatile *)Desc_ready_Wr) +#define bfin_read_Desc_ready_Wr() bfin_read16(Desc_ready_Wr) +#define bfin_write_Desc_ready_Wr(val) bfin_write16(Desc_ready_Wr, val) +#define pInterrupt_Stat_Wr ((uint16_t volatile *)Interrupt_Stat_Wr) +#define bfin_read_Interrupt_Stat_Wr() bfin_read16(Interrupt_Stat_Wr) +#define bfin_write_Interrupt_Stat_Wr(val) bfin_write16(Interrupt_Stat_Wr, val) +#define pCurrent_desc_Rd ((uint16_t volatile *)Current_desc_Rd) +#define bfin_read_Current_desc_Rd() bfin_read16(Current_desc_Rd) +#define bfin_write_Current_desc_Rd(val) bfin_write16(Current_desc_Rd, val) +#define pConfig_Rd ((uint16_t volatile *)Config_Rd) +#define bfin_read_Config_Rd() bfin_read16(Config_Rd) +#define bfin_write_Config_Rd(val) bfin_write16(Config_Rd, val) +#define pStart_page_Rd ((uint16_t volatile *)Start_page_Rd) +#define bfin_read_Start_page_Rd() bfin_read16(Start_page_Rd) +#define bfin_write_Start_page_Rd(val) bfin_write16(Start_page_Rd, val) +#define pStart_addr_Rd ((uint16_t volatile *)Start_addr_Rd) +#define bfin_read_Start_addr_Rd() bfin_read16(Start_addr_Rd) +#define bfin_write_Start_addr_Rd(val) bfin_write16(Start_addr_Rd, val) +#define pWord_count_Rd ((uint16_t volatile *)Word_count_Rd) +#define bfin_read_Word_count_Rd() bfin_read16(Word_count_Rd) +#define bfin_write_Word_count_Rd(val) bfin_write16(Word_count_Rd, val) +#define pNext_desc_Rd ((uint16_t volatile *)Next_desc_Rd) +#define bfin_read_Next_desc_Rd() bfin_read16(Next_desc_Rd) +#define bfin_write_Next_desc_Rd(val) bfin_write16(Next_desc_Rd, val) +#define pDesc_ready_Rd ((uint16_t volatile *)Desc_ready_Rd) +#define bfin_read_Desc_ready_Rd() bfin_read16(Desc_ready_Rd) +#define bfin_write_Desc_ready_Rd(val) bfin_write16(Desc_ready_Rd, val) +#define pInterrupt_Stat_Rd ((uint16_t volatile *)Interrupt_Stat_Rd) +#define bfin_read_Interrupt_Stat_Rd() bfin_read16(Interrupt_Stat_Rd) +#define bfin_write_Interrupt_Stat_Rd(val) bfin_write16(Interrupt_Stat_Rd, val) +#define pTSTATUS0 ((uint16_t volatile *)TSTATUS0) +#define bfin_read_TSTATUS0() bfin_read16(TSTATUS0) +#define bfin_write_TSTATUS0(val) bfin_write16(TSTATUS0, val) +#define pTSTATUS1 ((uint16_t volatile *)TSTATUS1) +#define bfin_read_TSTATUS1() bfin_read16(TSTATUS1) +#define bfin_write_TSTATUS1(val) bfin_write16(TSTATUS1, val) +#define pTSTATUS2 ((uint16_t volatile *)TSTATUS2) +#define bfin_read_TSTATUS2() bfin_read16(TSTATUS2) +#define bfin_write_TSTATUS2(val) bfin_write16(TSTATUS2, val) +#define pTSTATUS ((uint16_t volatile *)TSTATUS) +#define bfin_read_TSTATUS() bfin_read16(TSTATUS) +#define bfin_write_TSTATUS(val) bfin_write16(TSTATUS, val) +#define pTCONFIG0 ((uint16_t volatile *)TCONFIG0) +#define bfin_read_TCONFIG0() bfin_read16(TCONFIG0) +#define bfin_write_TCONFIG0(val) bfin_write16(TCONFIG0, val) +#define pTCOUNT0_LO ((uint16_t volatile *)TCOUNT0_LO) +#define bfin_read_TCOUNT0_LO() bfin_read16(TCOUNT0_LO) +#define bfin_write_TCOUNT0_LO(val) bfin_write16(TCOUNT0_LO, val) +#define pTCOUNT0_HI ((uint16_t volatile *)TCOUNT0_HI) +#define bfin_read_TCOUNT0_HI() bfin_read16(TCOUNT0_HI) +#define bfin_write_TCOUNT0_HI(val) bfin_write16(TCOUNT0_HI, val) +#define pTPERIOD0_LO ((uint16_t volatile *)TPERIOD0_LO) +#define bfin_read_TPERIOD0_LO() bfin_read16(TPERIOD0_LO) +#define bfin_write_TPERIOD0_LO(val) bfin_write16(TPERIOD0_LO, val) +#define pTPERIOD0_HI ((uint16_t volatile *)TPERIOD0_HI) +#define bfin_read_TPERIOD0_HI() bfin_read16(TPERIOD0_HI) +#define bfin_write_TPERIOD0_HI(val) bfin_write16(TPERIOD0_HI, val) +#define pTWIDTH0_LO ((uint16_t volatile *)TWIDTH0_LO) +#define bfin_read_TWIDTH0_LO() bfin_read16(TWIDTH0_LO) +#define bfin_write_TWIDTH0_LO(val) bfin_write16(TWIDTH0_LO, val) +#define pTWIDTH0_HI ((uint16_t volatile *)TWIDTH0_HI) +#define bfin_read_TWIDTH0_HI() bfin_read16(TWIDTH0_HI) +#define bfin_write_TWIDTH0_HI(val) bfin_write16(TWIDTH0_HI, val) +#define pTCONFIG1 ((uint16_t volatile *)TCONFIG1) +#define bfin_read_TCONFIG1() bfin_read16(TCONFIG1) +#define bfin_write_TCONFIG1(val) bfin_write16(TCONFIG1, val) +#define pTCOUNT1_LO ((uint16_t volatile *)TCOUNT1_LO) +#define bfin_read_TCOUNT1_LO() bfin_read16(TCOUNT1_LO) +#define bfin_write_TCOUNT1_LO(val) bfin_write16(TCOUNT1_LO, val) +#define pTCOUNT1_HI ((uint16_t volatile *)TCOUNT1_HI) +#define bfin_read_TCOUNT1_HI() bfin_read16(TCOUNT1_HI) +#define bfin_write_TCOUNT1_HI(val) bfin_write16(TCOUNT1_HI, val) +#define pTPERIOD1_LO ((uint16_t volatile *)TPERIOD1_LO) +#define bfin_read_TPERIOD1_LO() bfin_read16(TPERIOD1_LO) +#define bfin_write_TPERIOD1_LO(val) bfin_write16(TPERIOD1_LO, val) +#define pTPERIOD1_HI ((uint16_t volatile *)TPERIOD1_HI) +#define bfin_read_TPERIOD1_HI() bfin_read16(TPERIOD1_HI) +#define bfin_write_TPERIOD1_HI(val) bfin_write16(TPERIOD1_HI, val) +#define pTWIDTH1_LO ((uint16_t volatile *)TWIDTH1_LO) +#define bfin_read_TWIDTH1_LO() bfin_read16(TWIDTH1_LO) +#define bfin_write_TWIDTH1_LO(val) bfin_write16(TWIDTH1_LO, val) +#define pTWIDTH1_HI ((uint16_t volatile *)TWIDTH1_HI) +#define bfin_read_TWIDTH1_HI() bfin_read16(TWIDTH1_HI) +#define bfin_write_TWIDTH1_HI(val) bfin_write16(TWIDTH1_HI, val) +#define pTCONFIG2 ((uint16_t volatile *)TCONFIG2) +#define bfin_read_TCONFIG2() bfin_read16(TCONFIG2) +#define bfin_write_TCONFIG2(val) bfin_write16(TCONFIG2, val) +#define pTCOUNT2_LO ((uint16_t volatile *)TCOUNT2_LO) +#define bfin_read_TCOUNT2_LO() bfin_read16(TCOUNT2_LO) +#define bfin_write_TCOUNT2_LO(val) bfin_write16(TCOUNT2_LO, val) +#define pTCOUNT2_HI ((uint16_t volatile *)TCOUNT2_HI) +#define bfin_read_TCOUNT2_HI() bfin_read16(TCOUNT2_HI) +#define bfin_write_TCOUNT2_HI(val) bfin_write16(TCOUNT2_HI, val) +#define pTPERIOD2_LO ((uint16_t volatile *)TPERIOD2_LO) +#define bfin_read_TPERIOD2_LO() bfin_read16(TPERIOD2_LO) +#define bfin_write_TPERIOD2_LO(val) bfin_write16(TPERIOD2_LO, val) +#define pTPERIOD2_HI ((uint16_t volatile *)TPERIOD2_HI) +#define bfin_read_TPERIOD2_HI() bfin_read16(TPERIOD2_HI) +#define bfin_write_TPERIOD2_HI(val) bfin_write16(TPERIOD2_HI, val) +#define pTWIDTH2_LO ((uint16_t volatile *)TWIDTH2_LO) +#define bfin_read_TWIDTH2_LO() bfin_read16(TWIDTH2_LO) +#define bfin_write_TWIDTH2_LO(val) bfin_write16(TWIDTH2_LO, val) +#define pTWIDTH2_HI ((uint16_t volatile *)TWIDTH2_HI) +#define bfin_read_TWIDTH2_HI() bfin_read16(TWIDTH2_HI) +#define bfin_write_TWIDTH2_HI(val) bfin_write16(TWIDTH2_HI, val) +#define pSIC_RVECT ((uint16_t volatile *)SIC_RVECT) +#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT) +#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val) +#define pSIC_IAR0 ((uint32_t volatile *)SIC_IAR0) +#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) +#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val) +#define pSIC_IAR1 ((uint32_t volatile *)SIC_IAR1) +#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) +#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val) +#define pSIC_IAR2 ((uint32_t volatile *)SIC_IAR2) +#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2) +#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val) +#define pSIC_IMASK ((uint32_t volatile *)SIC_IMASK) +#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK) +#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val) +#define pSIC_ISR ((uint32_t volatile *)SIC_ISR) +#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR) +#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR, val) +#define pSIC_IWR ((uint32_t volatile *)SIC_IWR) +#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR) +#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR, val) +#define pUART0_THR ((uint16_t volatile *)UART0_THR) /* Transmit Holding */ +#define bfin_read_UART0_THR() bfin_read16(UART0_THR) +#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val) +#define pUART0_RBR ((uint16_t volatile *)UART0_RBR) /* Receive Buffer */ +#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR) +#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val) +#define pUART0_DLL ((uint16_t volatile *)UART0_DLL) /* Divisor Latch (Low-Byte) */ +#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL) +#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val) +#define pUART0_IER ((uint16_t volatile *)UART0_IER) /* Interrupt Enable */ +#define bfin_read_UART0_IER() bfin_read16(UART0_IER) +#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val) +#define pUART0_DLH ((uint16_t volatile *)UART0_DLH) /* Divisor Latch (High-Byte) */ +#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH) +#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val) +#define pUART0_IIR ((uint16_t volatile *)UART0_IIR) /* Interrupt Identification */ +#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR) +#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val) +#define pUART0_LCR ((uint16_t volatile *)UART0_LCR) /* Line Control */ +#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR) +#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val) +#define pUART0_MCR ((uint16_t volatile *)UART0_MCR) /* Module Control */ +#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR) +#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val) +#define pUART0_LSR ((uint16_t volatile *)UART0_LSR) /* Line Status */ +#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR) +#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val) +#define pUART0_MSR ((uint16_t volatile *)UART0_MSR) /* MSR Modem Status */ +#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR) +#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val) +#define pUART0_SCR ((uint16_t volatile *)UART0_SCR) /* SCR Scratch */ +#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR) +#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val) +#define pUART0_RX_CURR_PTR ((uint16_t volatile *)UART0_RX_CURR_PTR) +#define bfin_read_UART0_RX_CURR_PTR() bfin_read16(UART0_RX_CURR_PTR) +#define bfin_write_UART0_RX_CURR_PTR(val) bfin_write16(UART0_RX_CURR_PTR, val) +#define pUART0_RX_CONFIG_DMA ((uint16_t volatile *)UART0_RX_CONFIG_DMA) +#define bfin_read_UART0_RX_CONFIG_DMA() bfin_read16(UART0_RX_CONFIG_DMA) +#define bfin_write_UART0_RX_CONFIG_DMA(val) bfin_write16(UART0_RX_CONFIG_DMA, val) +#define pUART0_RX_START_PG ((uint16_t volatile *)UART0_RX_START_PG) +#define bfin_read_UART0_RX_START_PG() bfin_read16(UART0_RX_START_PG) +#define bfin_write_UART0_RX_START_PG(val) bfin_write16(UART0_RX_START_PG, val) +#define pUART0_RX_START_ADDR ((uint16_t volatile *)UART0_RX_START_ADDR) +#define bfin_read_UART0_RX_START_ADDR() bfin_read16(UART0_RX_START_ADDR) +#define bfin_write_UART0_RX_START_ADDR(val) bfin_write16(UART0_RX_START_ADDR, val) +#define pUART0_RX_COUNT ((uint16_t volatile *)UART0_RX_COUNT) +#define bfin_read_UART0_RX_COUNT() bfin_read16(UART0_RX_COUNT) +#define bfin_write_UART0_RX_COUNT(val) bfin_write16(UART0_RX_COUNT, val) +#define pUART0_RX_NEXT_DESCR ((uint16_t volatile *)UART0_RX_NEXT_DESCR) +#define bfin_read_UART0_RX_NEXT_DESCR() bfin_read16(UART0_RX_NEXT_DESCR) +#define bfin_write_UART0_RX_NEXT_DESCR(val) bfin_write16(UART0_RX_NEXT_DESCR, val) +#define pUART0_RX_DESCR_RDY ((uint16_t volatile *)UART0_RX_DESCR_RDY) +#define bfin_read_UART0_RX_DESCR_RDY() bfin_read16(UART0_RX_DESCR_RDY) +#define bfin_write_UART0_RX_DESCR_RDY(val) bfin_write16(UART0_RX_DESCR_RDY, val) +#define pUART0_RX_IRQSTAT ((uint16_t volatile *)UART0_RX_IRQSTAT) +#define bfin_read_UART0_RX_IRQSTAT() bfin_read16(UART0_RX_IRQSTAT) +#define bfin_write_UART0_RX_IRQSTAT(val) bfin_write16(UART0_RX_IRQSTAT, val) +#define pUART0_TX_CURR_PTR ((uint16_t volatile *)UART0_TX_CURR_PTR) +#define bfin_read_UART0_TX_CURR_PTR() bfin_read16(UART0_TX_CURR_PTR) +#define bfin_write_UART0_TX_CURR_PTR(val) bfin_write16(UART0_TX_CURR_PTR, val) +#define pUART0_TX_CONFIG_DMA ((uint16_t volatile *)UART0_TX_CONFIG_DMA) +#define bfin_read_UART0_TX_CONFIG_DMA() bfin_read16(UART0_TX_CONFIG_DMA) +#define bfin_write_UART0_TX_CONFIG_DMA(val) bfin_write16(UART0_TX_CONFIG_DMA, val) +#define pUART0_TX_START_PG ((uint16_t volatile *)UART0_TX_START_PG) +#define bfin_read_UART0_TX_START_PG() bfin_read16(UART0_TX_START_PG) +#define bfin_write_UART0_TX_START_PG(val) bfin_write16(UART0_TX_START_PG, val) +#define pUART0_TX_START_ADDR ((uint16_t volatile *)UART0_TX_START_ADDR) +#define bfin_read_UART0_TX_START_ADDR() bfin_read16(UART0_TX_START_ADDR) +#define bfin_write_UART0_TX_START_ADDR(val) bfin_write16(UART0_TX_START_ADDR, val) +#define pUART0_TX_COUNT ((uint16_t volatile *)UART0_TX_COUNT) +#define bfin_read_UART0_TX_COUNT() bfin_read16(UART0_TX_COUNT) +#define bfin_write_UART0_TX_COUNT(val) bfin_write16(UART0_TX_COUNT, val) +#define pUART0_TX_NEXT_DESCR ((uint16_t volatile *)UART0_TX_NEXT_DESCR) +#define bfin_read_UART0_TX_NEXT_DESCR() bfin_read16(UART0_TX_NEXT_DESCR) +#define bfin_write_UART0_TX_NEXT_DESCR(val) bfin_write16(UART0_TX_NEXT_DESCR, val) +#define pUART0_TX_DESCR_RDY ((uint16_t volatile *)UART0_TX_DESCR_RDY) +#define bfin_read_UART0_TX_DESCR_RDY() bfin_read16(UART0_TX_DESCR_RDY) +#define bfin_write_UART0_TX_DESCR_RDY(val) bfin_write16(UART0_TX_DESCR_RDY, val) +#define pUART0_TX_IRQSTAT ((uint16_t volatile *)UART0_TX_IRQSTAT) +#define bfin_read_UART0_TX_IRQSTAT() bfin_read16(UART0_TX_IRQSTAT) +#define bfin_write_UART0_TX_IRQSTAT(val) bfin_write16(UART0_TX_IRQSTAT, val) +#define pUART1_THR ((uint16_t volatile *)UART1_THR) /* Transmit Holding */ +#define bfin_read_UART1_THR() bfin_read16(UART1_THR) +#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val) +#define pUART1_RBR ((uint16_t volatile *)UART1_RBR) /* Receive Buffer */ +#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR) +#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val) +#define pUART1_DLL ((uint16_t volatile *)UART1_DLL) /* Divisor Latch (Low-Byte) */ +#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL) +#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val) +#define pUART1_IER ((uint16_t volatile *)UART1_IER) /* Interrupt Enable */ +#define bfin_read_UART1_IER() bfin_read16(UART1_IER) +#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val) +#define pUART1_DLH ((uint16_t volatile *)UART1_DLH) /* Divisor Latch (High-Byte) */ +#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH) +#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val) +#define pUART1_IIR ((uint16_t volatile *)UART1_IIR) /* Interrupt Identification */ +#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR) +#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val) +#define pUART1_LCR ((uint16_t volatile *)UART1_LCR) /* Line Control */ +#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR) +#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val) +#define pUART1_MCR ((uint16_t volatile *)UART1_MCR) /* Module Control */ +#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR) +#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val) +#define pUART1_LSR ((uint16_t volatile *)UART1_LSR) /* Line Status */ +#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR) +#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val) +#define pUART1_MSR ((uint16_t volatile *)UART1_MSR) /* MSR Modem Status */ +#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR) +#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val) +#define pUART1_SCR ((uint16_t volatile *)UART1_SCR) /* SCR Scratch */ +#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR) +#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val) +#define pUART1_RX_CURR_PTR ((uint16_t volatile *)UART1_RX_CURR_PTR) +#define bfin_read_UART1_RX_CURR_PTR() bfin_read16(UART1_RX_CURR_PTR) +#define bfin_write_UART1_RX_CURR_PTR(val) bfin_write16(UART1_RX_CURR_PTR, val) +#define pUART1_RX_CONFIG_DMA ((uint16_t volatile *)UART1_RX_CONFIG_DMA) +#define bfin_read_UART1_RX_CONFIG_DMA() bfin_read16(UART1_RX_CONFIG_DMA) +#define bfin_write_UART1_RX_CONFIG_DMA(val) bfin_write16(UART1_RX_CONFIG_DMA, val) +#define pUART1_RX_START_PG ((uint16_t volatile *)UART1_RX_START_PG) +#define bfin_read_UART1_RX_START_PG() bfin_read16(UART1_RX_START_PG) +#define bfin_write_UART1_RX_START_PG(val) bfin_write16(UART1_RX_START_PG, val) +#define pUART1_RX_START_ADDR ((uint16_t volatile *)UART1_RX_START_ADDR) +#define bfin_read_UART1_RX_START_ADDR() bfin_read16(UART1_RX_START_ADDR) +#define bfin_write_UART1_RX_START_ADDR(val) bfin_write16(UART1_RX_START_ADDR, val) +#define pUART1_RX_COUNT ((uint16_t volatile *)UART1_RX_COUNT) +#define bfin_read_UART1_RX_COUNT() bfin_read16(UART1_RX_COUNT) +#define bfin_write_UART1_RX_COUNT(val) bfin_write16(UART1_RX_COUNT, val) +#define pUART1_RX_NEXT_DESCR ((uint16_t volatile *)UART1_RX_NEXT_DESCR) +#define bfin_read_UART1_RX_NEXT_DESCR() bfin_read16(UART1_RX_NEXT_DESCR) +#define bfin_write_UART1_RX_NEXT_DESCR(val) bfin_write16(UART1_RX_NEXT_DESCR, val) +#define pUART1_RX_DESCR_RDY ((uint16_t volatile *)UART1_RX_DESCR_RDY) +#define bfin_read_UART1_RX_DESCR_RDY() bfin_read16(UART1_RX_DESCR_RDY) +#define bfin_write_UART1_RX_DESCR_RDY(val) bfin_write16(UART1_RX_DESCR_RDY, val) +#define pUART1_RX_IRQSTAT ((uint16_t volatile *)UART1_RX_IRQSTAT) +#define bfin_read_UART1_RX_IRQSTAT() bfin_read16(UART1_RX_IRQSTAT) +#define bfin_write_UART1_RX_IRQSTAT(val) bfin_write16(UART1_RX_IRQSTAT, val) +#define pUART1_TX_CURR_PTR ((uint16_t volatile *)UART1_TX_CURR_PTR) +#define bfin_read_UART1_TX_CURR_PTR() bfin_read16(UART1_TX_CURR_PTR) +#define bfin_write_UART1_TX_CURR_PTR(val) bfin_write16(UART1_TX_CURR_PTR, val) +#define pUART1_TX_CONFIG_DMA ((uint16_t volatile *)UART1_TX_CONFIG_DMA) +#define bfin_read_UART1_TX_CONFIG_DMA() bfin_read16(UART1_TX_CONFIG_DMA) +#define bfin_write_UART1_TX_CONFIG_DMA(val) bfin_write16(UART1_TX_CONFIG_DMA, val) +#define pUART1_TX_START_PG ((uint16_t volatile *)UART1_TX_START_PG) +#define bfin_read_UART1_TX_START_PG() bfin_read16(UART1_TX_START_PG) +#define bfin_write_UART1_TX_START_PG(val) bfin_write16(UART1_TX_START_PG, val) +#define pUART1_TX_START_ADDR ((uint16_t volatile *)UART1_TX_START_ADDR) +#define bfin_read_UART1_TX_START_ADDR() bfin_read16(UART1_TX_START_ADDR) +#define bfin_write_UART1_TX_START_ADDR(val) bfin_write16(UART1_TX_START_ADDR, val) +#define pUART1_TX_COUNT ((uint16_t volatile *)UART1_TX_COUNT) +#define bfin_read_UART1_TX_COUNT() bfin_read16(UART1_TX_COUNT) +#define bfin_write_UART1_TX_COUNT(val) bfin_write16(UART1_TX_COUNT, val) +#define pUART1_TX_NEXT_DESCR ((uint16_t volatile *)UART1_TX_NEXT_DESCR) +#define bfin_read_UART1_TX_NEXT_DESCR() bfin_read16(UART1_TX_NEXT_DESCR) +#define bfin_write_UART1_TX_NEXT_DESCR(val) bfin_write16(UART1_TX_NEXT_DESCR, val) +#define pUART1_TX_DESCR_RDY ((uint16_t volatile *)UART1_TX_DESCR_RDY) +#define bfin_read_UART1_TX_DESCR_RDY() bfin_read16(UART1_TX_DESCR_RDY) +#define bfin_write_UART1_TX_DESCR_RDY(val) bfin_write16(UART1_TX_DESCR_RDY, val) +#define pUART1_TX_IRQSTAT ((uint16_t volatile *)UART1_TX_IRQSTAT) +#define bfin_read_UART1_TX_IRQSTAT() bfin_read16(UART1_TX_IRQSTAT) +#define bfin_write_UART1_TX_IRQSTAT(val) bfin_write16(UART1_TX_IRQSTAT, val) +#define pPLL_CTL ((uint32_t volatile *)PLL_CTL) +#define bfin_read_PLL_CTL() bfin_read32(PLL_CTL) +#define bfin_write_PLL_CTL(val) bfin_write32(PLL_CTL, val) +#define pPLL_STAT ((uint32_t volatile *)PLL_STAT) +#define bfin_read_PLL_STAT() bfin_read32(PLL_STAT) +#define bfin_write_PLL_STAT(val) bfin_write32(PLL_STAT, val) +#define pPLL_LOCKCNT ((uint32_t volatile *)PLL_LOCKCNT) +#define bfin_read_PLL_LOCKCNT() bfin_read32(PLL_LOCKCNT) +#define bfin_write_PLL_LOCKCNT(val) bfin_write32(PLL_LOCKCNT, val) +#define pPLL_IOCK ((uint16_t volatile *)PLL_IOCK) +#define bfin_read_PLL_IOCK() bfin_read16(PLL_IOCK) +#define bfin_write_PLL_IOCK(val) bfin_write16(PLL_IOCK, val) +#define pSWRST ((uint16_t volatile *)SWRST) +#define bfin_read_SWRST() bfin_read16(SWRST) +#define bfin_write_SWRST(val) bfin_write16(SWRST, val) +#define pSYSCR ((uint32_t volatile *)SYSCR) +#define bfin_read_SYSCR() bfin_read32(SYSCR) +#define bfin_write_SYSCR(val) bfin_write32(SYSCR, val) +#define pDCPLB_STATUS ((uint32_t volatile *)DCPLB_STATUS) +#define bfin_read_DCPLB_STATUS() bfin_read32(DCPLB_STATUS) +#define bfin_write_DCPLB_STATUS(val) bfin_write32(DCPLB_STATUS, val) +#define pDCPLB_FAULT_ADDR ((uint32_t volatile *)DCPLB_FAULT_ADDR) +#define bfin_read_DCPLB_FAULT_ADDR() bfin_read32(DCPLB_FAULT_ADDR) +#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_write32(DCPLB_FAULT_ADDR, val) +#define pICPLB_STATUS ((uint32_t volatile *)ICPLB_STATUS) +#define bfin_read_ICPLB_STATUS() bfin_read32(ICPLB_STATUS) +#define bfin_write_ICPLB_STATUS(val) bfin_write32(ICPLB_STATUS, val) +#define pICPLB_FAULT_ADDR ((uint32_t volatile *)ICPLB_FAULT_ADDR) +#define bfin_read_ICPLB_FAULT_ADDR() bfin_read32(ICPLB_FAULT_ADDR) +#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR, val) +#define pCHIPID ((uint32_t volatile *)CHIPID) +#define bfin_read_CHIPID() bfin_read32(CHIPID) +#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val) +#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) +#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL) +#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val) +#define pTBUFSTAT ((uint32_t volatile *)TBUFSTAT) +#define bfin_read_TBUFSTAT() bfin_read32(TBUFSTAT) +#define bfin_write_TBUFSTAT(val) bfin_write32(TBUFSTAT, val) +#define pTBUF ((uint32_t volatile *)TBUF) +#define bfin_read_TBUF() bfin_read32(TBUF) +#define bfin_write_TBUF(val) bfin_write32(TBUF, val) +#define pPFCTL ((uint32_t volatile *)PFCTL) +#define bfin_read_PFCTL() bfin_read32(PFCTL) +#define bfin_write_PFCTL(val) bfin_write32(PFCTL, val) +#define pPFCNTR0 ((uint32_t volatile *)PFCNTR0) +#define bfin_read_PFCNTR0() bfin_read32(PFCNTR0) +#define bfin_write_PFCNTR0(val) bfin_write32(PFCNTR0, val) +#define pPFCNTR1 ((uint32_t volatile *)PFCNTR1) +#define bfin_read_PFCNTR1() bfin_read32(PFCNTR1) +#define bfin_write_PFCNTR1(val) bfin_write32(PFCNTR1, val) +#define pWDOG_CTL ((uint16_t volatile *)WDOG_CTL) +#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL) +#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val) +#define pWDOG_CNT ((uint32_t volatile *)WDOG_CNT) +#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT) +#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val) +#define pWDOG_STAT ((uint32_t volatile *)WDOG_STAT) +#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT) +#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val) +#define pRTC_STAT ((uint32_t volatile *)RTC_STAT) +#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT) +#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val) +#define pRTC_ICTL ((uint16_t volatile *)RTC_ICTL) +#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL) +#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val) +#define pRTC_ISTAT ((uint16_t volatile *)RTC_ISTAT) +#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT) +#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val) +#define pRTC_SWCNT ((uint16_t volatile *)RTC_SWCNT) +#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT) +#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val) +#define pRTC_ALARM ((uint32_t volatile *)RTC_ALARM) +#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM) +#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val) +#define pRTC_FAST ((uint16_t volatile *)RTC_FAST) +#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST) +#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val) +#define pUART0_IRCR ((uint16_t volatile *)UART0_IRCR) +#define bfin_read_UART0_IRCR() bfin_read16(UART0_IRCR) +#define bfin_write_UART0_IRCR(val) bfin_write16(UART0_IRCR, val) +#define pUART0_CURR_PTR_RX ((uint16_t volatile *)UART0_CURR_PTR_RX) +#define bfin_read_UART0_CURR_PTR_RX() bfin_read16(UART0_CURR_PTR_RX) +#define bfin_write_UART0_CURR_PTR_RX(val) bfin_write16(UART0_CURR_PTR_RX, val) +#define pUART0_CONFIG_RX ((uint16_t volatile *)UART0_CONFIG_RX) +#define bfin_read_UART0_CONFIG_RX() bfin_read16(UART0_CONFIG_RX) +#define bfin_write_UART0_CONFIG_RX(val) bfin_write16(UART0_CONFIG_RX, val) +#define pUART0_START_ADDR_HI_RX ((uint16_t volatile *)UART0_START_ADDR_HI_RX) +#define bfin_read_UART0_START_ADDR_HI_RX() bfin_read16(UART0_START_ADDR_HI_RX) +#define bfin_write_UART0_START_ADDR_HI_RX(val) bfin_write16(UART0_START_ADDR_HI_RX, val) +#define pUART0_START_ADDR_LO_RX ((uint16_t volatile *)UART0_START_ADDR_LO_RX) +#define bfin_read_UART0_START_ADDR_LO_RX() bfin_read16(UART0_START_ADDR_LO_RX) +#define bfin_write_UART0_START_ADDR_LO_RX(val) bfin_write16(UART0_START_ADDR_LO_RX, val) +#define pUART0_COUNT_RX ((uint16_t volatile *)UART0_COUNT_RX) +#define bfin_read_UART0_COUNT_RX() bfin_read16(UART0_COUNT_RX) +#define bfin_write_UART0_COUNT_RX(val) bfin_write16(UART0_COUNT_RX, val) +#define pUART0_NEXT_DESCR_RX ((uint16_t volatile *)UART0_NEXT_DESCR_RX) +#define bfin_read_UART0_NEXT_DESCR_RX() bfin_read16(UART0_NEXT_DESCR_RX) +#define bfin_write_UART0_NEXT_DESCR_RX(val) bfin_write16(UART0_NEXT_DESCR_RX, val) +#define pUART0_DESCR_RDY_RX ((uint16_t volatile *)UART0_DESCR_RDY_RX) +#define bfin_read_UART0_DESCR_RDY_RX() bfin_read16(UART0_DESCR_RDY_RX) +#define bfin_write_UART0_DESCR_RDY_RX(val) bfin_write16(UART0_DESCR_RDY_RX, val) +#define pUART0_IRQSTAT_RX ((uint16_t volatile *)UART0_IRQSTAT_RX) +#define bfin_read_UART0_IRQSTAT_RX() bfin_read16(UART0_IRQSTAT_RX) +#define bfin_write_UART0_IRQSTAT_RX(val) bfin_write16(UART0_IRQSTAT_RX, val) +#define pUART0_CURR_PTR_TX ((uint16_t volatile *)UART0_CURR_PTR_TX) +#define bfin_read_UART0_CURR_PTR_TX() bfin_read16(UART0_CURR_PTR_TX) +#define bfin_write_UART0_CURR_PTR_TX(val) bfin_write16(UART0_CURR_PTR_TX, val) +#define pUART0_CONFIG_TX ((uint16_t volatile *)UART0_CONFIG_TX) +#define bfin_read_UART0_CONFIG_TX() bfin_read16(UART0_CONFIG_TX) +#define bfin_write_UART0_CONFIG_TX(val) bfin_write16(UART0_CONFIG_TX, val) +#define pUART0_START_ADDR_HI_TX ((uint16_t volatile *)UART0_START_ADDR_HI_TX) +#define bfin_read_UART0_START_ADDR_HI_TX() bfin_read16(UART0_START_ADDR_HI_TX) +#define bfin_write_UART0_START_ADDR_HI_TX(val) bfin_write16(UART0_START_ADDR_HI_TX, val) +#define pUART0_START_ADDR_LO_TX ((uint16_t volatile *)UART0_START_ADDR_LO_TX) +#define bfin_read_UART0_START_ADDR_LO_TX() bfin_read16(UART0_START_ADDR_LO_TX) +#define bfin_write_UART0_START_ADDR_LO_TX(val) bfin_write16(UART0_START_ADDR_LO_TX, val) +#define pUART0_COUNT_TX ((uint16_t volatile *)UART0_COUNT_TX) +#define bfin_read_UART0_COUNT_TX() bfin_read16(UART0_COUNT_TX) +#define bfin_write_UART0_COUNT_TX(val) bfin_write16(UART0_COUNT_TX, val) +#define pUART0_NEXT_DESCR_TX ((uint16_t volatile *)UART0_NEXT_DESCR_TX) +#define bfin_read_UART0_NEXT_DESCR_TX() bfin_read16(UART0_NEXT_DESCR_TX) +#define bfin_write_UART0_NEXT_DESCR_TX(val) bfin_write16(UART0_NEXT_DESCR_TX, val) +#define pUART0_DESCR_RDY_TX ((uint16_t volatile *)UART0_DESCR_RDY_TX) +#define bfin_read_UART0_DESCR_RDY_TX() bfin_read16(UART0_DESCR_RDY_TX) +#define bfin_write_UART0_DESCR_RDY_TX(val) bfin_write16(UART0_DESCR_RDY_TX, val) +#define pUART0_IRQSTAT_TX ((uint16_t volatile *)UART0_IRQSTAT_TX) +#define bfin_read_UART0_IRQSTAT_TX() bfin_read16(UART0_IRQSTAT_TX) +#define bfin_write_UART0_IRQSTAT_TX(val) bfin_write16(UART0_IRQSTAT_TX, val) +#define pUART1_CURR_PTR_RX ((uint16_t volatile *)UART1_CURR_PTR_RX) +#define bfin_read_UART1_CURR_PTR_RX() bfin_read16(UART1_CURR_PTR_RX) +#define bfin_write_UART1_CURR_PTR_RX(val) bfin_write16(UART1_CURR_PTR_RX, val) +#define pUART1_CONFIG_RX ((uint16_t volatile *)UART1_CONFIG_RX) +#define bfin_read_UART1_CONFIG_RX() bfin_read16(UART1_CONFIG_RX) +#define bfin_write_UART1_CONFIG_RX(val) bfin_write16(UART1_CONFIG_RX, val) +#define pUART1_START_ADDR_HI_RX ((uint16_t volatile *)UART1_START_ADDR_HI_RX) +#define bfin_read_UART1_START_ADDR_HI_RX() bfin_read16(UART1_START_ADDR_HI_RX) +#define bfin_write_UART1_START_ADDR_HI_RX(val) bfin_write16(UART1_START_ADDR_HI_RX, val) +#define pUART1_START_ADDR_LO_RX ((uint16_t volatile *)UART1_START_ADDR_LO_RX) +#define bfin_read_UART1_START_ADDR_LO_RX() bfin_read16(UART1_START_ADDR_LO_RX) +#define bfin_write_UART1_START_ADDR_LO_RX(val) bfin_write16(UART1_START_ADDR_LO_RX, val) +#define pUART1_COUNT_RX ((uint16_t volatile *)UART1_COUNT_RX) +#define bfin_read_UART1_COUNT_RX() bfin_read16(UART1_COUNT_RX) +#define bfin_write_UART1_COUNT_RX(val) bfin_write16(UART1_COUNT_RX, val) +#define pUART1_NEXT_DESCR_RX ((uint16_t volatile *)UART1_NEXT_DESCR_RX) +#define bfin_read_UART1_NEXT_DESCR_RX() bfin_read16(UART1_NEXT_DESCR_RX) +#define bfin_write_UART1_NEXT_DESCR_RX(val) bfin_write16(UART1_NEXT_DESCR_RX, val) +#define pUART1_DESCR_RDY_RX ((uint16_t volatile *)UART1_DESCR_RDY_RX) +#define bfin_read_UART1_DESCR_RDY_RX() bfin_read16(UART1_DESCR_RDY_RX) +#define bfin_write_UART1_DESCR_RDY_RX(val) bfin_write16(UART1_DESCR_RDY_RX, val) +#define pUART1_IRQSTAT_RX ((uint16_t volatile *)UART1_IRQSTAT_RX) +#define bfin_read_UART1_IRQSTAT_RX() bfin_read16(UART1_IRQSTAT_RX) +#define bfin_write_UART1_IRQSTAT_RX(val) bfin_write16(UART1_IRQSTAT_RX, val) +#define pUART1_CURR_PTR_TX ((uint16_t volatile *)UART1_CURR_PTR_TX) +#define bfin_read_UART1_CURR_PTR_TX() bfin_read16(UART1_CURR_PTR_TX) +#define bfin_write_UART1_CURR_PTR_TX(val) bfin_write16(UART1_CURR_PTR_TX, val) +#define pUART1_CONFIG_TX ((uint16_t volatile *)UART1_CONFIG_TX) +#define bfin_read_UART1_CONFIG_TX() bfin_read16(UART1_CONFIG_TX) +#define bfin_write_UART1_CONFIG_TX(val) bfin_write16(UART1_CONFIG_TX, val) +#define pUART1_START_ADDR_HI_TX ((uint16_t volatile *)UART1_START_ADDR_HI_TX) +#define bfin_read_UART1_START_ADDR_HI_TX() bfin_read16(UART1_START_ADDR_HI_TX) +#define bfin_write_UART1_START_ADDR_HI_TX(val) bfin_write16(UART1_START_ADDR_HI_TX, val) +#define pUART1_START_ADDR_LO_TX ((uint16_t volatile *)UART1_START_ADDR_LO_TX) +#define bfin_read_UART1_START_ADDR_LO_TX() bfin_read16(UART1_START_ADDR_LO_TX) +#define bfin_write_UART1_START_ADDR_LO_TX(val) bfin_write16(UART1_START_ADDR_LO_TX, val) +#define pUART1_COUNT_TX ((uint16_t volatile *)UART1_COUNT_TX) +#define bfin_read_UART1_COUNT_TX() bfin_read16(UART1_COUNT_TX) +#define bfin_write_UART1_COUNT_TX(val) bfin_write16(UART1_COUNT_TX, val) +#define pUART1_NEXT_DESCR_TX ((uint16_t volatile *)UART1_NEXT_DESCR_TX) +#define bfin_read_UART1_NEXT_DESCR_TX() bfin_read16(UART1_NEXT_DESCR_TX) +#define bfin_write_UART1_NEXT_DESCR_TX(val) bfin_write16(UART1_NEXT_DESCR_TX, val) +#define pUART1_DESCR_RDY_TX ((uint16_t volatile *)UART1_DESCR_RDY_TX) +#define bfin_read_UART1_DESCR_RDY_TX() bfin_read16(UART1_DESCR_RDY_TX) +#define bfin_write_UART1_DESCR_RDY_TX(val) bfin_write16(UART1_DESCR_RDY_TX, val) +#define pUART1_IRQSTAT_TX ((uint16_t volatile *)UART1_IRQSTAT_TX) +#define bfin_read_UART1_IRQSTAT_TX() bfin_read16(UART1_IRQSTAT_TX) +#define bfin_write_UART1_IRQSTAT_TX(val) bfin_write16(UART1_IRQSTAT_TX, val) +#define pTIMER0_STATUS ((uint16_t volatile *)TIMER0_STATUS) +#define bfin_read_TIMER0_STATUS() bfin_read16(TIMER0_STATUS) +#define bfin_write_TIMER0_STATUS(val) bfin_write16(TIMER0_STATUS, val) +#define pTIMER0_CONFIG ((uint16_t volatile *)TIMER0_CONFIG) +#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG) +#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val) +#define pTIMER0_COUNTER_LO ((uint16_t volatile *)TIMER0_COUNTER_LO) +#define bfin_read_TIMER0_COUNTER_LO() bfin_read16(TIMER0_COUNTER_LO) +#define bfin_write_TIMER0_COUNTER_LO(val) bfin_write16(TIMER0_COUNTER_LO, val) +#define pTIMER0_COUNTER_HI ((uint16_t volatile *)TIMER0_COUNTER_HI) +#define bfin_read_TIMER0_COUNTER_HI() bfin_read16(TIMER0_COUNTER_HI) +#define bfin_write_TIMER0_COUNTER_HI(val) bfin_write16(TIMER0_COUNTER_HI, val) +#define pTIMER0_PERIOD_LO ((uint16_t volatile *)TIMER0_PERIOD_LO) +#define bfin_read_TIMER0_PERIOD_LO() bfin_read16(TIMER0_PERIOD_LO) +#define bfin_write_TIMER0_PERIOD_LO(val) bfin_write16(TIMER0_PERIOD_LO, val) +#define pTIMER0_PERIOD_HI ((uint16_t volatile *)TIMER0_PERIOD_HI) +#define bfin_read_TIMER0_PERIOD_HI() bfin_read16(TIMER0_PERIOD_HI) +#define bfin_write_TIMER0_PERIOD_HI(val) bfin_write16(TIMER0_PERIOD_HI, val) +#define pTIMER0_WIDTH_LO ((uint16_t volatile *)TIMER0_WIDTH_LO) +#define bfin_read_TIMER0_WIDTH_LO() bfin_read16(TIMER0_WIDTH_LO) +#define bfin_write_TIMER0_WIDTH_LO(val) bfin_write16(TIMER0_WIDTH_LO, val) +#define pTIMER0_WIDTH_HI ((uint16_t volatile *)TIMER0_WIDTH_HI) +#define bfin_read_TIMER0_WIDTH_HI() bfin_read16(TIMER0_WIDTH_HI) +#define bfin_write_TIMER0_WIDTH_HI(val) bfin_write16(TIMER0_WIDTH_HI, val) +#define pTIMER1_STATUS ((uint16_t volatile *)TIMER1_STATUS) +#define bfin_read_TIMER1_STATUS() bfin_read16(TIMER1_STATUS) +#define bfin_write_TIMER1_STATUS(val) bfin_write16(TIMER1_STATUS, val) +#define pTIMER1_CONFIG ((uint16_t volatile *)TIMER1_CONFIG) +#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG) +#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val) +#define pTIMER1_COUNTER_LO ((uint16_t volatile *)TIMER1_COUNTER_LO) +#define bfin_read_TIMER1_COUNTER_LO() bfin_read16(TIMER1_COUNTER_LO) +#define bfin_write_TIMER1_COUNTER_LO(val) bfin_write16(TIMER1_COUNTER_LO, val) +#define pTIMER1_COUNTER_HI ((uint16_t volatile *)TIMER1_COUNTER_HI) +#define bfin_read_TIMER1_COUNTER_HI() bfin_read16(TIMER1_COUNTER_HI) +#define bfin_write_TIMER1_COUNTER_HI(val) bfin_write16(TIMER1_COUNTER_HI, val) +#define pTIMER1_PERIOD_LO ((uint16_t volatile *)TIMER1_PERIOD_LO) +#define bfin_read_TIMER1_PERIOD_LO() bfin_read16(TIMER1_PERIOD_LO) +#define bfin_write_TIMER1_PERIOD_LO(val) bfin_write16(TIMER1_PERIOD_LO, val) +#define pTIMER1_PERIOD_HI ((uint16_t volatile *)TIMER1_PERIOD_HI) +#define bfin_read_TIMER1_PERIOD_HI() bfin_read16(TIMER1_PERIOD_HI) +#define bfin_write_TIMER1_PERIOD_HI(val) bfin_write16(TIMER1_PERIOD_HI, val) +#define pTIMER1_WIDTH_LO ((uint16_t volatile *)TIMER1_WIDTH_LO) +#define bfin_read_TIMER1_WIDTH_LO() bfin_read16(TIMER1_WIDTH_LO) +#define bfin_write_TIMER1_WIDTH_LO(val) bfin_write16(TIMER1_WIDTH_LO, val) +#define pTIMER1_WIDTH_HI ((uint16_t volatile *)TIMER1_WIDTH_HI) +#define bfin_read_TIMER1_WIDTH_HI() bfin_read16(TIMER1_WIDTH_HI) +#define bfin_write_TIMER1_WIDTH_HI(val) bfin_write16(TIMER1_WIDTH_HI, val) +#define pTIMER2_STATUS ((uint16_t volatile *)TIMER2_STATUS) +#define bfin_read_TIMER2_STATUS() bfin_read16(TIMER2_STATUS) +#define bfin_write_TIMER2_STATUS(val) bfin_write16(TIMER2_STATUS, val) +#define pTIMER2_CONFIG ((uint16_t volatile *)TIMER2_CONFIG) +#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG) +#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val) +#define pTIMER2_COUNTER_LO ((uint16_t volatile *)TIMER2_COUNTER_LO) +#define bfin_read_TIMER2_COUNTER_LO() bfin_read16(TIMER2_COUNTER_LO) +#define bfin_write_TIMER2_COUNTER_LO(val) bfin_write16(TIMER2_COUNTER_LO, val) +#define pTIMER2_COUNTER_HI ((uint16_t volatile *)TIMER2_COUNTER_HI) +#define bfin_read_TIMER2_COUNTER_HI() bfin_read16(TIMER2_COUNTER_HI) +#define bfin_write_TIMER2_COUNTER_HI(val) bfin_write16(TIMER2_COUNTER_HI, val) +#define pTIMER2_PERIOD_LO ((uint16_t volatile *)TIMER2_PERIOD_LO) +#define bfin_read_TIMER2_PERIOD_LO() bfin_read16(TIMER2_PERIOD_LO) +#define bfin_write_TIMER2_PERIOD_LO(val) bfin_write16(TIMER2_PERIOD_LO, val) +#define pTIMER2_PERIOD_HI ((uint16_t volatile *)TIMER2_PERIOD_HI) +#define bfin_read_TIMER2_PERIOD_HI() bfin_read16(TIMER2_PERIOD_HI) +#define bfin_write_TIMER2_PERIOD_HI(val) bfin_write16(TIMER2_PERIOD_HI, val) +#define pTIMER2_WIDTH_LO ((uint16_t volatile *)TIMER2_WIDTH_LO) +#define bfin_read_TIMER2_WIDTH_LO() bfin_read16(TIMER2_WIDTH_LO) +#define bfin_write_TIMER2_WIDTH_LO(val) bfin_write16(TIMER2_WIDTH_LO, val) +#define pTIMER2_WIDTH_HI ((uint16_t volatile *)TIMER2_WIDTH_HI) +#define bfin_read_TIMER2_WIDTH_HI() bfin_read16(TIMER2_WIDTH_HI) +#define bfin_write_TIMER2_WIDTH_HI(val) bfin_write16(TIMER2_WIDTH_HI, val) +#define pFIO_DIR ((uint16_t volatile *)FIO_DIR) +#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR) +#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR, val) +#define pFIO_FLAG_C ((uint16_t volatile *)FIO_FLAG_C) +#define bfin_read_FIO_FLAG_C() bfin_read16(FIO_FLAG_C) +#define bfin_write_FIO_FLAG_C(val) bfin_write16(FIO_FLAG_C, val) +#define pFIO_FLAG_S ((uint16_t volatile *)FIO_FLAG_S) +#define bfin_read_FIO_FLAG_S() bfin_read16(FIO_FLAG_S) +#define bfin_write_FIO_FLAG_S(val) bfin_write16(FIO_FLAG_S, val) +#define pFIO_MASKA_C ((uint16_t volatile *)FIO_MASKA_C) +#define bfin_read_FIO_MASKA_C() bfin_read16(FIO_MASKA_C) +#define bfin_write_FIO_MASKA_C(val) bfin_write16(FIO_MASKA_C, val) +#define pFIO_MASKA_S ((uint16_t volatile *)FIO_MASKA_S) +#define bfin_read_FIO_MASKA_S() bfin_read16(FIO_MASKA_S) +#define bfin_write_FIO_MASKA_S(val) bfin_write16(FIO_MASKA_S, val) +#define pFIO_MASKB_C ((uint16_t volatile *)FIO_MASKB_C) +#define bfin_read_FIO_MASKB_C() bfin_read16(FIO_MASKB_C) +#define bfin_write_FIO_MASKB_C(val) bfin_write16(FIO_MASKB_C, val) +#define pFIO_MASKB_S ((uint16_t volatile *)FIO_MASKB_S) +#define bfin_read_FIO_MASKB_S() bfin_read16(FIO_MASKB_S) +#define bfin_write_FIO_MASKB_S(val) bfin_write16(FIO_MASKB_S, val) +#define pFIO_POLAR ((uint16_t volatile *)FIO_POLAR) +#define bfin_read_FIO_POLAR() bfin_read16(FIO_POLAR) +#define bfin_write_FIO_POLAR(val) bfin_write16(FIO_POLAR, val) +#define pFIO_EDGE ((uint16_t volatile *)FIO_EDGE) +#define bfin_read_FIO_EDGE() bfin_read16(FIO_EDGE) +#define bfin_write_FIO_EDGE(val) bfin_write16(FIO_EDGE, val) +#define pFIO_BOTH ((uint16_t volatile *)FIO_BOTH) +#define bfin_read_FIO_BOTH() bfin_read16(FIO_BOTH) +#define bfin_write_FIO_BOTH(val) bfin_write16(FIO_BOTH, val) +#define pSPORT0_TX_CONFIG ((uint16_t volatile *)SPORT0_TX_CONFIG) +#define bfin_read_SPORT0_TX_CONFIG() bfin_read16(SPORT0_TX_CONFIG) +#define bfin_write_SPORT0_TX_CONFIG(val) bfin_write16(SPORT0_TX_CONFIG, val) +#define pSPORT0_RX_CONFIG ((uint16_t volatile *)SPORT0_RX_CONFIG) +#define bfin_read_SPORT0_RX_CONFIG() bfin_read16(SPORT0_RX_CONFIG) +#define bfin_write_SPORT0_RX_CONFIG(val) bfin_write16(SPORT0_RX_CONFIG, val) +#define pSPORT0_TX ((uint16_t volatile *)SPORT0_TX) +#define bfin_read_SPORT0_TX() bfin_read16(SPORT0_TX) +#define bfin_write_SPORT0_TX(val) bfin_write16(SPORT0_TX, val) +#define pSPORT0_RX ((uint16_t volatile *)SPORT0_RX) +#define bfin_read_SPORT0_RX() bfin_read16(SPORT0_RX) +#define bfin_write_SPORT0_RX(val) bfin_write16(SPORT0_RX, val) +#define pSPORT0_TSCLKDIV ((uint16_t volatile *)SPORT0_TSCLKDIV) +#define bfin_read_SPORT0_TSCLKDIV() bfin_read16(SPORT0_TSCLKDIV) +#define bfin_write_SPORT0_TSCLKDIV(val) bfin_write16(SPORT0_TSCLKDIV, val) +#define pSPORT0_RSCLKDIV ((uint16_t volatile *)SPORT0_RSCLKDIV) +#define bfin_read_SPORT0_RSCLKDIV() bfin_read16(SPORT0_RSCLKDIV) +#define bfin_write_SPORT0_RSCLKDIV(val) bfin_write16(SPORT0_RSCLKDIV, val) +#define pSPORT0_TFSDIV ((uint16_t volatile *)SPORT0_TFSDIV) +#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV) +#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val) +#define pSPORT0_RFSDIV ((uint16_t volatile *)SPORT0_RFSDIV) +#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV) +#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val) +#define pSPORT0_STAT ((uint16_t volatile *)SPORT0_STAT) +#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT) +#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val) +#define pSPORT0_MTCS0 ((uint16_t volatile *)SPORT0_MTCS0) +#define bfin_read_SPORT0_MTCS0() bfin_read16(SPORT0_MTCS0) +#define bfin_write_SPORT0_MTCS0(val) bfin_write16(SPORT0_MTCS0, val) +#define pSPORT0_MTCS1 ((uint16_t volatile *)SPORT0_MTCS1) +#define bfin_read_SPORT0_MTCS1() bfin_read16(SPORT0_MTCS1) +#define bfin_write_SPORT0_MTCS1(val) bfin_write16(SPORT0_MTCS1, val) +#define pSPORT0_MTCS2 ((uint16_t volatile *)SPORT0_MTCS2) +#define bfin_read_SPORT0_MTCS2() bfin_read16(SPORT0_MTCS2) +#define bfin_write_SPORT0_MTCS2(val) bfin_write16(SPORT0_MTCS2, val) +#define pSPORT0_MTCS3 ((uint16_t volatile *)SPORT0_MTCS3) +#define bfin_read_SPORT0_MTCS3() bfin_read16(SPORT0_MTCS3) +#define bfin_write_SPORT0_MTCS3(val) bfin_write16(SPORT0_MTCS3, val) +#define pSPORT0_MTCS4 ((uint16_t volatile *)SPORT0_MTCS4) +#define bfin_read_SPORT0_MTCS4() bfin_read16(SPORT0_MTCS4) +#define bfin_write_SPORT0_MTCS4(val) bfin_write16(SPORT0_MTCS4, val) +#define pSPORT0_MTCS5 ((uint16_t volatile *)SPORT0_MTCS5) +#define bfin_read_SPORT0_MTCS5() bfin_read16(SPORT0_MTCS5) +#define bfin_write_SPORT0_MTCS5(val) bfin_write16(SPORT0_MTCS5, val) +#define pSPORT0_MTCS6 ((uint16_t volatile *)SPORT0_MTCS6) +#define bfin_read_SPORT0_MTCS6() bfin_read16(SPORT0_MTCS6) +#define bfin_write_SPORT0_MTCS6(val) bfin_write16(SPORT0_MTCS6, val) +#define pSPORT0_MTCS7 ((uint16_t volatile *)SPORT0_MTCS7) +#define bfin_read_SPORT0_MTCS7() bfin_read16(SPORT0_MTCS7) +#define bfin_write_SPORT0_MTCS7(val) bfin_write16(SPORT0_MTCS7, val) +#define pSPORT0_MRCS0 ((uint16_t volatile *)SPORT0_MRCS0) +#define bfin_read_SPORT0_MRCS0() bfin_read16(SPORT0_MRCS0) +#define bfin_write_SPORT0_MRCS0(val) bfin_write16(SPORT0_MRCS0, val) +#define pSPORT0_MRCS1 ((uint16_t volatile *)SPORT0_MRCS1) +#define bfin_read_SPORT0_MRCS1() bfin_read16(SPORT0_MRCS1) +#define bfin_write_SPORT0_MRCS1(val) bfin_write16(SPORT0_MRCS1, val) +#define pSPORT0_MRCS2 ((uint16_t volatile *)SPORT0_MRCS2) +#define bfin_read_SPORT0_MRCS2() bfin_read16(SPORT0_MRCS2) +#define bfin_write_SPORT0_MRCS2(val) bfin_write16(SPORT0_MRCS2, val) +#define pSPORT0_MRCS3 ((uint16_t volatile *)SPORT0_MRCS3) +#define bfin_read_SPORT0_MRCS3() bfin_read16(SPORT0_MRCS3) +#define bfin_write_SPORT0_MRCS3(val) bfin_write16(SPORT0_MRCS3, val) +#define pSPORT0_MRCS4 ((uint16_t volatile *)SPORT0_MRCS4) +#define bfin_read_SPORT0_MRCS4() bfin_read16(SPORT0_MRCS4) +#define bfin_write_SPORT0_MRCS4(val) bfin_write16(SPORT0_MRCS4, val) +#define pSPORT0_MRCS5 ((uint16_t volatile *)SPORT0_MRCS5) +#define bfin_read_SPORT0_MRCS5() bfin_read16(SPORT0_MRCS5) +#define bfin_write_SPORT0_MRCS5(val) bfin_write16(SPORT0_MRCS5, val) +#define pSPORT0_MRCS6 ((uint16_t volatile *)SPORT0_MRCS6) +#define bfin_read_SPORT0_MRCS6() bfin_read16(SPORT0_MRCS6) +#define bfin_write_SPORT0_MRCS6(val) bfin_write16(SPORT0_MRCS6, val) +#define pSPORT0_MRCS7 ((uint16_t volatile *)SPORT0_MRCS7) +#define bfin_read_SPORT0_MRCS7() bfin_read16(SPORT0_MRCS7) +#define bfin_write_SPORT0_MRCS7(val) bfin_write16(SPORT0_MRCS7, val) +#define pSPORT0_MCMC1 ((uint16_t volatile *)SPORT0_MCMC1) +#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1) +#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val) +#define pSPORT0_MCMC2 ((uint16_t volatile *)SPORT0_MCMC2) +#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2) +#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val) +#define pSPORT0_CURR_PTR_RX ((uint16_t volatile *)SPORT0_CURR_PTR_RX) +#define bfin_read_SPORT0_CURR_PTR_RX() bfin_read16(SPORT0_CURR_PTR_RX) +#define bfin_write_SPORT0_CURR_PTR_RX(val) bfin_write16(SPORT0_CURR_PTR_RX, val) +#define pSPORT0_CONFIG_DMA_RX ((uint16_t volatile *)SPORT0_CONFIG_DMA_RX) +#define bfin_read_SPORT0_CONFIG_DMA_RX() bfin_read16(SPORT0_CONFIG_DMA_RX) +#define bfin_write_SPORT0_CONFIG_DMA_RX(val) bfin_write16(SPORT0_CONFIG_DMA_RX, val) +#define pSPORT0_START_ADDR_HI_RX ((uint16_t volatile *)SPORT0_START_ADDR_HI_RX) +#define bfin_read_SPORT0_START_ADDR_HI_RX() bfin_read16(SPORT0_START_ADDR_HI_RX) +#define bfin_write_SPORT0_START_ADDR_HI_RX(val) bfin_write16(SPORT0_START_ADDR_HI_RX, val) +#define pSPORT0_START_ADDR_LO_RX ((uint16_t volatile *)SPORT0_START_ADDR_LO_RX) +#define bfin_read_SPORT0_START_ADDR_LO_RX() bfin_read16(SPORT0_START_ADDR_LO_RX) +#define bfin_write_SPORT0_START_ADDR_LO_RX(val) bfin_write16(SPORT0_START_ADDR_LO_RX, val) +#define pSPORT0_COUNT_RX ((uint16_t volatile *)SPORT0_COUNT_RX) +#define bfin_read_SPORT0_COUNT_RX() bfin_read16(SPORT0_COUNT_RX) +#define bfin_write_SPORT0_COUNT_RX(val) bfin_write16(SPORT0_COUNT_RX, val) +#define pSPORT0_NEXT_DESCR_RX ((uint16_t volatile *)SPORT0_NEXT_DESCR_RX) +#define bfin_read_SPORT0_NEXT_DESCR_RX() bfin_read16(SPORT0_NEXT_DESCR_RX) +#define bfin_write_SPORT0_NEXT_DESCR_RX(val) bfin_write16(SPORT0_NEXT_DESCR_RX, val) +#define pSPORT0_DESCR_RDY_RX ((uint16_t volatile *)SPORT0_DESCR_RDY_RX) +#define bfin_read_SPORT0_DESCR_RDY_RX() bfin_read16(SPORT0_DESCR_RDY_RX) +#define bfin_write_SPORT0_DESCR_RDY_RX(val) bfin_write16(SPORT0_DESCR_RDY_RX, val) +#define pSPORT0_IRQSTAT_RX ((uint16_t volatile *)SPORT0_IRQSTAT_RX) +#define bfin_read_SPORT0_IRQSTAT_RX() bfin_read16(SPORT0_IRQSTAT_RX) +#define bfin_write_SPORT0_IRQSTAT_RX(val) bfin_write16(SPORT0_IRQSTAT_RX, val) +#define pSPORT0_CURR_PTR_TX ((uint16_t volatile *)SPORT0_CURR_PTR_TX) +#define bfin_read_SPORT0_CURR_PTR_TX() bfin_read16(SPORT0_CURR_PTR_TX) +#define bfin_write_SPORT0_CURR_PTR_TX(val) bfin_write16(SPORT0_CURR_PTR_TX, val) +#define pSPORT0_CONFIG_DMA_TX ((uint16_t volatile *)SPORT0_CONFIG_DMA_TX) +#define bfin_read_SPORT0_CONFIG_DMA_TX() bfin_read16(SPORT0_CONFIG_DMA_TX) +#define bfin_write_SPORT0_CONFIG_DMA_TX(val) bfin_write16(SPORT0_CONFIG_DMA_TX, val) +#define pSPORT0_START_ADDR_HI_TX ((uint16_t volatile *)SPORT0_START_ADDR_HI_TX) +#define bfin_read_SPORT0_START_ADDR_HI_TX() bfin_read16(SPORT0_START_ADDR_HI_TX) +#define bfin_write_SPORT0_START_ADDR_HI_TX(val) bfin_write16(SPORT0_START_ADDR_HI_TX, val) +#define pSPORT0_START_ADDR_LO_TX ((uint16_t volatile *)SPORT0_START_ADDR_LO_TX) +#define bfin_read_SPORT0_START_ADDR_LO_TX() bfin_read16(SPORT0_START_ADDR_LO_TX) +#define bfin_write_SPORT0_START_ADDR_LO_TX(val) bfin_write16(SPORT0_START_ADDR_LO_TX, val) +#define pSPORT0_COUNT_TX ((uint16_t volatile *)SPORT0_COUNT_TX) +#define bfin_read_SPORT0_COUNT_TX() bfin_read16(SPORT0_COUNT_TX) +#define bfin_write_SPORT0_COUNT_TX(val) bfin_write16(SPORT0_COUNT_TX, val) +#define pSPORT0_NEXT_DESCR_TX ((uint16_t volatile *)SPORT0_NEXT_DESCR_TX) +#define bfin_read_SPORT0_NEXT_DESCR_TX() bfin_read16(SPORT0_NEXT_DESCR_TX) +#define bfin_write_SPORT0_NEXT_DESCR_TX(val) bfin_write16(SPORT0_NEXT_DESCR_TX, val) +#define pSPORT0_DESCR_RDY_TX ((uint16_t volatile *)SPORT0_DESCR_RDY_TX) +#define bfin_read_SPORT0_DESCR_RDY_TX() bfin_read16(SPORT0_DESCR_RDY_TX) +#define bfin_write_SPORT0_DESCR_RDY_TX(val) bfin_write16(SPORT0_DESCR_RDY_TX, val) +#define pSPORT0_IRQSTAT_TX ((uint16_t volatile *)SPORT0_IRQSTAT_TX) +#define bfin_read_SPORT0_IRQSTAT_TX() bfin_read16(SPORT0_IRQSTAT_TX) +#define bfin_write_SPORT0_IRQSTAT_TX(val) bfin_write16(SPORT0_IRQSTAT_TX, val) +#define pSPORT1_TX_CONFIG ((uint16_t volatile *)SPORT1_TX_CONFIG) +#define bfin_read_SPORT1_TX_CONFIG() bfin_read16(SPORT1_TX_CONFIG) +#define bfin_write_SPORT1_TX_CONFIG(val) bfin_write16(SPORT1_TX_CONFIG, val) +#define pSPORT1_RX_CONFIG ((uint16_t volatile *)SPORT1_RX_CONFIG) +#define bfin_read_SPORT1_RX_CONFIG() bfin_read16(SPORT1_RX_CONFIG) +#define bfin_write_SPORT1_RX_CONFIG(val) bfin_write16(SPORT1_RX_CONFIG, val) +#define pSPORT1_TX ((uint16_t volatile *)SPORT1_TX) +#define bfin_read_SPORT1_TX() bfin_read16(SPORT1_TX) +#define bfin_write_SPORT1_TX(val) bfin_write16(SPORT1_TX, val) +#define pSPORT1_RX ((uint16_t volatile *)SPORT1_RX) +#define bfin_read_SPORT1_RX() bfin_read16(SPORT1_RX) +#define bfin_write_SPORT1_RX(val) bfin_write16(SPORT1_RX, val) +#define pSPORT1_TSCLKDIV ((uint16_t volatile *)SPORT1_TSCLKDIV) +#define bfin_read_SPORT1_TSCLKDIV() bfin_read16(SPORT1_TSCLKDIV) +#define bfin_write_SPORT1_TSCLKDIV(val) bfin_write16(SPORT1_TSCLKDIV, val) +#define pSPORT1_RSCLKDIV ((uint16_t volatile *)SPORT1_RSCLKDIV) +#define bfin_read_SPORT1_RSCLKDIV() bfin_read16(SPORT1_RSCLKDIV) +#define bfin_write_SPORT1_RSCLKDIV(val) bfin_write16(SPORT1_RSCLKDIV, val) +#define pSPORT1_TFSDIV ((uint16_t volatile *)SPORT1_TFSDIV) +#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV) +#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val) +#define pSPORT1_RFSDIV ((uint16_t volatile *)SPORT1_RFSDIV) +#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV) +#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val) +#define pSPORT1_STAT ((uint16_t volatile *)SPORT1_STAT) +#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT) +#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val) +#define pSPORT1_MTCS0 ((uint16_t volatile *)SPORT1_MTCS0) +#define bfin_read_SPORT1_MTCS0() bfin_read16(SPORT1_MTCS0) +#define bfin_write_SPORT1_MTCS0(val) bfin_write16(SPORT1_MTCS0, val) +#define pSPORT1_MTCS1 ((uint16_t volatile *)SPORT1_MTCS1) +#define bfin_read_SPORT1_MTCS1() bfin_read16(SPORT1_MTCS1) +#define bfin_write_SPORT1_MTCS1(val) bfin_write16(SPORT1_MTCS1, val) +#define pSPORT1_MTCS2 ((uint16_t volatile *)SPORT1_MTCS2) +#define bfin_read_SPORT1_MTCS2() bfin_read16(SPORT1_MTCS2) +#define bfin_write_SPORT1_MTCS2(val) bfin_write16(SPORT1_MTCS2, val) +#define pSPORT1_MTCS3 ((uint16_t volatile *)SPORT1_MTCS3) +#define bfin_read_SPORT1_MTCS3() bfin_read16(SPORT1_MTCS3) +#define bfin_write_SPORT1_MTCS3(val) bfin_write16(SPORT1_MTCS3, val) +#define pSPORT1_MTCS4 ((uint16_t volatile *)SPORT1_MTCS4) +#define bfin_read_SPORT1_MTCS4() bfin_read16(SPORT1_MTCS4) +#define bfin_write_SPORT1_MTCS4(val) bfin_write16(SPORT1_MTCS4, val) +#define pSPORT1_MTCS5 ((uint16_t volatile *)SPORT1_MTCS5) +#define bfin_read_SPORT1_MTCS5() bfin_read16(SPORT1_MTCS5) +#define bfin_write_SPORT1_MTCS5(val) bfin_write16(SPORT1_MTCS5, val) +#define pSPORT1_MTCS6 ((uint16_t volatile *)SPORT1_MTCS6) +#define bfin_read_SPORT1_MTCS6() bfin_read16(SPORT1_MTCS6) +#define bfin_write_SPORT1_MTCS6(val) bfin_write16(SPORT1_MTCS6, val) +#define pSPORT1_MTCS7 ((uint16_t volatile *)SPORT1_MTCS7) +#define bfin_read_SPORT1_MTCS7() bfin_read16(SPORT1_MTCS7) +#define bfin_write_SPORT1_MTCS7(val) bfin_write16(SPORT1_MTCS7, val) +#define pSPORT1_MRCS0 ((uint16_t volatile *)SPORT1_MRCS0) +#define bfin_read_SPORT1_MRCS0() bfin_read16(SPORT1_MRCS0) +#define bfin_write_SPORT1_MRCS0(val) bfin_write16(SPORT1_MRCS0, val) +#define pSPORT1_MRCS1 ((uint16_t volatile *)SPORT1_MRCS1) +#define bfin_read_SPORT1_MRCS1() bfin_read16(SPORT1_MRCS1) +#define bfin_write_SPORT1_MRCS1(val) bfin_write16(SPORT1_MRCS1, val) +#define pSPORT1_MRCS2 ((uint16_t volatile *)SPORT1_MRCS2) +#define bfin_read_SPORT1_MRCS2() bfin_read16(SPORT1_MRCS2) +#define bfin_write_SPORT1_MRCS2(val) bfin_write16(SPORT1_MRCS2, val) +#define pSPORT1_MRCS3 ((uint16_t volatile *)SPORT1_MRCS3) +#define bfin_read_SPORT1_MRCS3() bfin_read16(SPORT1_MRCS3) +#define bfin_write_SPORT1_MRCS3(val) bfin_write16(SPORT1_MRCS3, val) +#define pSPORT1_MRCS4 ((uint16_t volatile *)SPORT1_MRCS4) +#define bfin_read_SPORT1_MRCS4() bfin_read16(SPORT1_MRCS4) +#define bfin_write_SPORT1_MRCS4(val) bfin_write16(SPORT1_MRCS4, val) +#define pSPORT1_MRCS5 ((uint16_t volatile *)SPORT1_MRCS5) +#define bfin_read_SPORT1_MRCS5() bfin_read16(SPORT1_MRCS5) +#define bfin_write_SPORT1_MRCS5(val) bfin_write16(SPORT1_MRCS5, val) +#define pSPORT1_MRCS6 ((uint16_t volatile *)SPORT1_MRCS6) +#define bfin_read_SPORT1_MRCS6() bfin_read16(SPORT1_MRCS6) +#define bfin_write_SPORT1_MRCS6(val) bfin_write16(SPORT1_MRCS6, val) +#define pSPORT1_MRCS7 ((uint16_t volatile *)SPORT1_MRCS7) +#define bfin_read_SPORT1_MRCS7() bfin_read16(SPORT1_MRCS7) +#define bfin_write_SPORT1_MRCS7(val) bfin_write16(SPORT1_MRCS7, val) +#define pSPORT1_MCMC1 ((uint16_t volatile *)SPORT1_MCMC1) +#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1) +#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val) +#define pSPORT1_MCMC2 ((uint16_t volatile *)SPORT1_MCMC2) +#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2) +#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val) +#define pSPORT1_CURR_PTR_RX ((uint16_t volatile *)SPORT1_CURR_PTR_RX) +#define bfin_read_SPORT1_CURR_PTR_RX() bfin_read16(SPORT1_CURR_PTR_RX) +#define bfin_write_SPORT1_CURR_PTR_RX(val) bfin_write16(SPORT1_CURR_PTR_RX, val) +#define pSPORT1_CONFIG_DMA_RX ((uint16_t volatile *)SPORT1_CONFIG_DMA_RX) +#define bfin_read_SPORT1_CONFIG_DMA_RX() bfin_read16(SPORT1_CONFIG_DMA_RX) +#define bfin_write_SPORT1_CONFIG_DMA_RX(val) bfin_write16(SPORT1_CONFIG_DMA_RX, val) +#define pSPORT1_START_ADDR_HI_RX ((uint16_t volatile *)SPORT1_START_ADDR_HI_RX) +#define bfin_read_SPORT1_START_ADDR_HI_RX() bfin_read16(SPORT1_START_ADDR_HI_RX) +#define bfin_write_SPORT1_START_ADDR_HI_RX(val) bfin_write16(SPORT1_START_ADDR_HI_RX, val) +#define pSPORT1_START_ADDR_LO_RX ((uint16_t volatile *)SPORT1_START_ADDR_LO_RX) +#define bfin_read_SPORT1_START_ADDR_LO_RX() bfin_read16(SPORT1_START_ADDR_LO_RX) +#define bfin_write_SPORT1_START_ADDR_LO_RX(val) bfin_write16(SPORT1_START_ADDR_LO_RX, val) +#define pSPORT1_COUNT_RX ((uint16_t volatile *)SPORT1_COUNT_RX) +#define bfin_read_SPORT1_COUNT_RX() bfin_read16(SPORT1_COUNT_RX) +#define bfin_write_SPORT1_COUNT_RX(val) bfin_write16(SPORT1_COUNT_RX, val) +#define pSPORT1_NEXT_DESCR_RX ((uint16_t volatile *)SPORT1_NEXT_DESCR_RX) +#define bfin_read_SPORT1_NEXT_DESCR_RX() bfin_read16(SPORT1_NEXT_DESCR_RX) +#define bfin_write_SPORT1_NEXT_DESCR_RX(val) bfin_write16(SPORT1_NEXT_DESCR_RX, val) +#define pSPORT1_DESCR_RDY_RX ((uint16_t volatile *)SPORT1_DESCR_RDY_RX) +#define bfin_read_SPORT1_DESCR_RDY_RX() bfin_read16(SPORT1_DESCR_RDY_RX) +#define bfin_write_SPORT1_DESCR_RDY_RX(val) bfin_write16(SPORT1_DESCR_RDY_RX, val) +#define pSPORT1_IRQSTAT_RX ((uint16_t volatile *)SPORT1_IRQSTAT_RX) +#define bfin_read_SPORT1_IRQSTAT_RX() bfin_read16(SPORT1_IRQSTAT_RX) +#define bfin_write_SPORT1_IRQSTAT_RX(val) bfin_write16(SPORT1_IRQSTAT_RX, val) +#define pSPORT1_CURR_PTR_TX ((uint16_t volatile *)SPORT1_CURR_PTR_TX) +#define bfin_read_SPORT1_CURR_PTR_TX() bfin_read16(SPORT1_CURR_PTR_TX) +#define bfin_write_SPORT1_CURR_PTR_TX(val) bfin_write16(SPORT1_CURR_PTR_TX, val) +#define pSPORT1_CONFIG_DMA_TX ((uint16_t volatile *)SPORT1_CONFIG_DMA_TX) +#define bfin_read_SPORT1_CONFIG_DMA_TX() bfin_read16(SPORT1_CONFIG_DMA_TX) +#define bfin_write_SPORT1_CONFIG_DMA_TX(val) bfin_write16(SPORT1_CONFIG_DMA_TX, val) +#define pSPORT1_START_ADDR_HI_TX ((uint16_t volatile *)SPORT1_START_ADDR_HI_TX) +#define bfin_read_SPORT1_START_ADDR_HI_TX() bfin_read16(SPORT1_START_ADDR_HI_TX) +#define bfin_write_SPORT1_START_ADDR_HI_TX(val) bfin_write16(SPORT1_START_ADDR_HI_TX, val) +#define pSPORT1_START_ADDR_LO_TX ((uint16_t volatile *)SPORT1_START_ADDR_LO_TX) +#define bfin_read_SPORT1_START_ADDR_LO_TX() bfin_read16(SPORT1_START_ADDR_LO_TX) +#define bfin_write_SPORT1_START_ADDR_LO_TX(val) bfin_write16(SPORT1_START_ADDR_LO_TX, val) +#define pSPORT1_COUNT_TX ((uint16_t volatile *)SPORT1_COUNT_TX) +#define bfin_read_SPORT1_COUNT_TX() bfin_read16(SPORT1_COUNT_TX) +#define bfin_write_SPORT1_COUNT_TX(val) bfin_write16(SPORT1_COUNT_TX, val) +#define pSPORT1_NEXT_DESCR_TX ((uint16_t volatile *)SPORT1_NEXT_DESCR_TX) +#define bfin_read_SPORT1_NEXT_DESCR_TX() bfin_read16(SPORT1_NEXT_DESCR_TX) +#define bfin_write_SPORT1_NEXT_DESCR_TX(val) bfin_write16(SPORT1_NEXT_DESCR_TX, val) +#define pSPORT1_DESCR_RDY_TX ((uint16_t volatile *)SPORT1_DESCR_RDY_TX) +#define bfin_read_SPORT1_DESCR_RDY_TX() bfin_read16(SPORT1_DESCR_RDY_TX) +#define bfin_write_SPORT1_DESCR_RDY_TX(val) bfin_write16(SPORT1_DESCR_RDY_TX, val) +#define pSPORT1_IRQSTAT_TX ((uint16_t volatile *)SPORT1_IRQSTAT_TX) +#define bfin_read_SPORT1_IRQSTAT_TX() bfin_read16(SPORT1_IRQSTAT_TX) +#define bfin_write_SPORT1_IRQSTAT_TX(val) bfin_write16(SPORT1_IRQSTAT_TX, val) +#define pSPI0_CTL ((uint16_t volatile *)SPI0_CTL) +#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL) +#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val) +#define pSPI0_FLG ((uint16_t volatile *)SPI0_FLG) +#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG) +#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val) +#define pSPI0_ST ((uint16_t volatile *)SPI0_ST) +#define bfin_read_SPI0_ST() bfin_read16(SPI0_ST) +#define bfin_write_SPI0_ST(val) bfin_write16(SPI0_ST, val) +#define pSPI0_BAUD ((uint16_t volatile *)SPI0_BAUD) +#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD) +#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val) +#define pSPI0_SHADOW ((uint16_t volatile *)SPI0_SHADOW) +#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW) +#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val) +#define pSPI0_CURR_PTR ((uint16_t volatile *)SPI0_CURR_PTR) +#define bfin_read_SPI0_CURR_PTR() bfin_read16(SPI0_CURR_PTR) +#define bfin_write_SPI0_CURR_PTR(val) bfin_write16(SPI0_CURR_PTR, val) +#define pSPI0_CONFIG ((uint16_t volatile *)SPI0_CONFIG) +#define bfin_read_SPI0_CONFIG() bfin_read16(SPI0_CONFIG) +#define bfin_write_SPI0_CONFIG(val) bfin_write16(SPI0_CONFIG, val) +#define pSPI0_START_ADDR_HI ((uint16_t volatile *)SPI0_START_ADDR_HI) +#define bfin_read_SPI0_START_ADDR_HI() bfin_read16(SPI0_START_ADDR_HI) +#define bfin_write_SPI0_START_ADDR_HI(val) bfin_write16(SPI0_START_ADDR_HI, val) +#define pSPI0_START_ADDR_LO ((uint16_t volatile *)SPI0_START_ADDR_LO) +#define bfin_read_SPI0_START_ADDR_LO() bfin_read16(SPI0_START_ADDR_LO) +#define bfin_write_SPI0_START_ADDR_LO(val) bfin_write16(SPI0_START_ADDR_LO, val) +#define pSPI0_COUNT ((uint16_t volatile *)SPI0_COUNT) +#define bfin_read_SPI0_COUNT() bfin_read16(SPI0_COUNT) +#define bfin_write_SPI0_COUNT(val) bfin_write16(SPI0_COUNT, val) +#define pSPI0_NEXT_DESCR ((uint16_t volatile *)SPI0_NEXT_DESCR) +#define bfin_read_SPI0_NEXT_DESCR() bfin_read16(SPI0_NEXT_DESCR) +#define bfin_write_SPI0_NEXT_DESCR(val) bfin_write16(SPI0_NEXT_DESCR, val) +#define pSPI0_DESCR_RDY ((uint16_t volatile *)SPI0_DESCR_RDY) +#define bfin_read_SPI0_DESCR_RDY() bfin_read16(SPI0_DESCR_RDY) +#define bfin_write_SPI0_DESCR_RDY(val) bfin_write16(SPI0_DESCR_RDY, val) +#define pSPI0_DMA_INT ((uint16_t volatile *)SPI0_DMA_INT) +#define bfin_read_SPI0_DMA_INT() bfin_read16(SPI0_DMA_INT) +#define bfin_write_SPI0_DMA_INT(val) bfin_write16(SPI0_DMA_INT, val) +#define pSPI1_CTL ((uint16_t volatile *)SPI1_CTL) +#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL) +#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val) +#define pSPI1_FLG ((uint16_t volatile *)SPI1_FLG) +#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG) +#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val) +#define pSPI1_ST ((uint16_t volatile *)SPI1_ST) +#define bfin_read_SPI1_ST() bfin_read16(SPI1_ST) +#define bfin_write_SPI1_ST(val) bfin_write16(SPI1_ST, val) +#define pSPI1_BAUD ((uint16_t volatile *)SPI1_BAUD) +#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD) +#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val) +#define pSPI1_SHADOW ((uint16_t volatile *)SPI1_SHADOW) +#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW) +#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val) +#define pSPI1_CURR_PTR ((uint16_t volatile *)SPI1_CURR_PTR) +#define bfin_read_SPI1_CURR_PTR() bfin_read16(SPI1_CURR_PTR) +#define bfin_write_SPI1_CURR_PTR(val) bfin_write16(SPI1_CURR_PTR, val) +#define pSPI1_CONFIG ((uint16_t volatile *)SPI1_CONFIG) +#define bfin_read_SPI1_CONFIG() bfin_read16(SPI1_CONFIG) +#define bfin_write_SPI1_CONFIG(val) bfin_write16(SPI1_CONFIG, val) +#define pSPI1_START_ADDR_HI ((uint16_t volatile *)SPI1_START_ADDR_HI) +#define bfin_read_SPI1_START_ADDR_HI() bfin_read16(SPI1_START_ADDR_HI) +#define bfin_write_SPI1_START_ADDR_HI(val) bfin_write16(SPI1_START_ADDR_HI, val) +#define pSPI1_START_ADDR_LO ((uint16_t volatile *)SPI1_START_ADDR_LO) +#define bfin_read_SPI1_START_ADDR_LO() bfin_read16(SPI1_START_ADDR_LO) +#define bfin_write_SPI1_START_ADDR_LO(val) bfin_write16(SPI1_START_ADDR_LO, val) +#define pSPI1_COUNT ((uint16_t volatile *)SPI1_COUNT) +#define bfin_read_SPI1_COUNT() bfin_read16(SPI1_COUNT) +#define bfin_write_SPI1_COUNT(val) bfin_write16(SPI1_COUNT, val) +#define pSPI1_NEXT_DESCR ((uint16_t volatile *)SPI1_NEXT_DESCR) +#define bfin_read_SPI1_NEXT_DESCR() bfin_read16(SPI1_NEXT_DESCR) +#define bfin_write_SPI1_NEXT_DESCR(val) bfin_write16(SPI1_NEXT_DESCR, val) +#define pSPI1_DESCR_RDY ((uint16_t volatile *)SPI1_DESCR_RDY) +#define bfin_read_SPI1_DESCR_RDY() bfin_read16(SPI1_DESCR_RDY) +#define bfin_write_SPI1_DESCR_RDY(val) bfin_write16(SPI1_DESCR_RDY, val) +#define pSPI1_DMA_INT ((uint16_t volatile *)SPI1_DMA_INT) +#define bfin_read_SPI1_DMA_INT() bfin_read16(SPI1_DMA_INT) +#define bfin_write_SPI1_DMA_INT(val) bfin_write16(SPI1_DMA_INT, val) +#define pMDD_DCP ((uint16_t volatile *)MDD_DCP) +#define bfin_read_MDD_DCP() bfin_read16(MDD_DCP) +#define bfin_write_MDD_DCP(val) bfin_write16(MDD_DCP, val) +#define pMDD_DCFG ((uint16_t volatile *)MDD_DCFG) +#define bfin_read_MDD_DCFG() bfin_read16(MDD_DCFG) +#define bfin_write_MDD_DCFG(val) bfin_write16(MDD_DCFG, val) +#define pMDD_DSAH ((uint16_t volatile *)MDD_DSAH) +#define bfin_read_MDD_DSAH() bfin_read16(MDD_DSAH) +#define bfin_write_MDD_DSAH(val) bfin_write16(MDD_DSAH, val) +#define pMDD_DSAL ((uint16_t volatile *)MDD_DSAL) +#define bfin_read_MDD_DSAL() bfin_read16(MDD_DSAL) +#define bfin_write_MDD_DSAL(val) bfin_write16(MDD_DSAL, val) +#define pMDD_DCT ((uint16_t volatile *)MDD_DCT) +#define bfin_read_MDD_DCT() bfin_read16(MDD_DCT) +#define bfin_write_MDD_DCT(val) bfin_write16(MDD_DCT, val) +#define pMDD_DND ((uint16_t volatile *)MDD_DND) +#define bfin_read_MDD_DND() bfin_read16(MDD_DND) +#define bfin_write_MDD_DND(val) bfin_write16(MDD_DND, val) +#define pMDD_DDR ((uint16_t volatile *)MDD_DDR) +#define bfin_read_MDD_DDR() bfin_read16(MDD_DDR) +#define bfin_write_MDD_DDR(val) bfin_write16(MDD_DDR, val) +#define pMDD_DI ((uint16_t volatile *)MDD_DI) +#define bfin_read_MDD_DI() bfin_read16(MDD_DI) +#define bfin_write_MDD_DI(val) bfin_write16(MDD_DI, val) +#define pMDS_DCP ((uint16_t volatile *)MDS_DCP) +#define bfin_read_MDS_DCP() bfin_read16(MDS_DCP) +#define bfin_write_MDS_DCP(val) bfin_write16(MDS_DCP, val) +#define pMDS_DCFG ((uint16_t volatile *)MDS_DCFG) +#define bfin_read_MDS_DCFG() bfin_read16(MDS_DCFG) +#define bfin_write_MDS_DCFG(val) bfin_write16(MDS_DCFG, val) +#define pMDS_DSAH ((uint16_t volatile *)MDS_DSAH) +#define bfin_read_MDS_DSAH() bfin_read16(MDS_DSAH) +#define bfin_write_MDS_DSAH(val) bfin_write16(MDS_DSAH, val) +#define pMDS_DSAL ((uint16_t volatile *)MDS_DSAL) +#define bfin_read_MDS_DSAL() bfin_read16(MDS_DSAL) +#define bfin_write_MDS_DSAL(val) bfin_write16(MDS_DSAL, val) +#define pMDS_DCT ((uint16_t volatile *)MDS_DCT) +#define bfin_read_MDS_DCT() bfin_read16(MDS_DCT) +#define bfin_write_MDS_DCT(val) bfin_write16(MDS_DCT, val) +#define pMDS_DND ((uint16_t volatile *)MDS_DND) +#define bfin_read_MDS_DND() bfin_read16(MDS_DND) +#define bfin_write_MDS_DND(val) bfin_write16(MDS_DND, val) +#define pMDS_DDR ((uint16_t volatile *)MDS_DDR) +#define bfin_read_MDS_DDR() bfin_read16(MDS_DDR) +#define bfin_write_MDS_DDR(val) bfin_write16(MDS_DDR, val) +#define pMDS_DI ((uint16_t volatile *)MDS_DI) +#define bfin_read_MDS_DI() bfin_read16(MDS_DI) +#define bfin_write_MDS_DI(val) bfin_write16(MDS_DI, val) +#define pEBIU_AMGCTL ((uint16_t volatile *)EBIU_AMGCTL) +#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL) +#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val) +#define pEBIU_AMBCTL0 ((uint32_t volatile *)EBIU_AMBCTL0) +#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0) +#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val) +#define pEBIU_AMBCTL1 ((uint32_t volatile *)EBIU_AMBCTL1) +#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1) +#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val) +#define pDMA_DBP ((uint16_t volatile *)DMA_DBP) +#define bfin_read_DMA_DBP() bfin_read16(DMA_DBP) +#define bfin_write_DMA_DBP(val) bfin_write16(DMA_DBP, val) +#define pDB_ACOMP ((uint32_t volatile *)DB_ACOMP) +#define bfin_read_DB_ACOMP() bfin_read32(DB_ACOMP) +#define bfin_write_DB_ACOMP(val) bfin_write32(DB_ACOMP, val) +#define pDB_CCOMP ((uint32_t volatile *)DB_CCOMP) +#define bfin_read_DB_CCOMP() bfin_read32(DB_CCOMP) +#define bfin_write_DB_CCOMP(val) bfin_write32(DB_CCOMP, val) +#define pEBIU_SDGCTL ((uint32_t volatile *)EBIU_SDGCTL) +#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL) +#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val) +#define pEBIU_SDBCTL ((uint32_t volatile *)EBIU_SDBCTL) +#define bfin_read_EBIU_SDBCTL() bfin_read32(EBIU_SDBCTL) +#define bfin_write_EBIU_SDBCTL(val) bfin_write32(EBIU_SDBCTL, val) +#define pEBIU_SDRRC ((uint16_t volatile *)EBIU_SDRRC) +#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC) +#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val) +#define pEBIU_SDSTAT ((uint16_t volatile *)EBIU_SDSTAT) +#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT) +#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val) + +#endif /* __BFIN_CDEF_ADSP_BF535_proc__ */ diff --git a/u-boot-2008.10/include/asm-blackfin/mach-bf579/BF579_def.h b/u-boot-2008.10/include/asm-blackfin/mach-bf579/BF579_def.h new file mode 100644 index 0000000..a9f089b --- /dev/null +++ b/u-boot-2008.10/include/asm-blackfin/mach-bf579/BF579_def.h @@ -0,0 +1,663 @@ +/* DO NOT EDIT THIS FILE + * Automatically generated by generate-def-headers.xsl + * DO NOT EDIT THIS FILE + */ + +#ifndef __BFIN_DEF_ADSP_BF535_proc__ +#define __BFIN_DEF_ADSP_BF535_proc__ + +#include "ADSP-FRIO-core_def.h" + +#define ILAT 0xFFE0210C /* Interrupt Latch Register */ +#define IMASK 0xFFE02104 /* Interrupt Mask Register */ +#define IPEND 0xFFE02108 /* Interrupt Pending Register */ +#define TCNTL 0xFFE03000 +#define TPERIOD 0xFFE03004 +#define TSCALE 0xFFE03008 +#define TCOUNT 0xFFE0300C +#define SRAM_BASE_ADDR 0xFFE00000 +#define DMEM_CONTROL 0xFFE00004 +#define DCPLB_FAULT_STATUS 0xFFE00008 +#define DCPLB_FAULT_ADDR 0xFFE0000C +#define DCPLB_ADDR0 0xFFE00100 +#define DCPLB_ADDR1 0xFFE00104 +#define DCPLB_ADDR2 0xFFE00108 +#define DCPLB_ADDR3 0xFFE0010C +#define DCPLB_ADDR4 0xFFE00110 +#define DCPLB_ADDR5 0xFFE00114 +#define DCPLB_ADDR6 0xFFE00118 +#define DCPLB_ADDR7 0xFFE0011C +#define DCPLB_ADDR8 0xFFE00120 +#define DCPLB_ADDR9 0xFFE00124 +#define DCPLB_ADDR10 0xFFE00128 +#define DCPLB_ADDR11 0xFFE0012C +#define DCPLB_ADDR12 0xFFE00130 +#define DCPLB_ADDR13 0xFFE00134 +#define DCPLB_ADDR14 0xFFE00138 +#define DCPLB_ADDR15 0xFFE0013C +#define DCPLB_DATA0 0xFFE00200 +#define DCPLB_DATA1 0xFFE00204 +#define DCPLB_DATA2 0xFFE00208 +#define DCPLB_DATA3 0xFFE0020C +#define DCPLB_DATA4 0xFFE00210 +#define DCPLB_DATA5 0xFFE00214 +#define DCPLB_DATA6 0xFFE00218 +#define DCPLB_DATA7 0xFFE0021C +#define DCPLB_DATA8 0xFFE00220 +#define DCPLB_DATA9 0xFFE00224 +#define DCPLB_DATA10 0xFFE00228 +#define DCPLB_DATA11 0xFFE0022C +#define DCPLB_DATA12 0xFFE00230 +#define DCPLB_DATA13 0xFFE00234 +#define DCPLB_DATA14 0xFFE00238 +#define DCPLB_DATA15 0xFFE0023C +#define DTEST_COMMAND 0xFFE00300 +#define DTEST_DATA0 0xFFE00400 +#define DTEST_DATA1 0xFFE00404 +#define EVT0 0xFFE02000 +#define EVT1 0xFFE02004 +#define EVT2 0xFFE02008 +#define EVT3 0xFFE0200C +#define EVT4 0xFFE02010 +#define EVT5 0xFFE02014 +#define EVT6 0xFFE02018 +#define EVT7 0xFFE0201C +#define EVT8 0xFFE02020 +#define EVT9 0xFFE02024 +#define EVT10 0xFFE02028 +#define EVT11 0xFFE0202C +#define EVT12 0xFFE02030 +#define EVT13 0xFFE02034 +#define EVT14 0xFFE02038 +#define EVT15 0xFFE0203C +#define IMEM_CONTROL 0xFFE01004 +#define ICPLB_FAULT_STATUS 0xFFE01008 +#define ICPLB_FAULT_ADDR 0xFFE0100C +#define ICPLB_ADDR0 0xFFE01100 +#define ICPLB_ADDR1 0xFFE01104 +#define ICPLB_ADDR2 0xFFE01108 +#define ICPLB_ADDR3 0xFFE0110C +#define ICPLB_ADDR4 0xFFE01110 +#define ICPLB_ADDR5 0xFFE01114 +#define ICPLB_ADDR6 0xFFE01118 +#define ICPLB_ADDR7 0xFFE0111C +#define ICPLB_ADDR8 0xFFE01120 +#define ICPLB_ADDR9 0xFFE01124 +#define ICPLB_ADDR10 0xFFE01128 +#define ICPLB_ADDR11 0xFFE0112C +#define ICPLB_ADDR12 0xFFE01130 +#define ICPLB_ADDR13 0xFFE01134 +#define ICPLB_ADDR14 0xFFE01138 +#define ICPLB_ADDR15 0xFFE0113C +#define ICPLB_DATA0 0xFFE01200 +#define ICPLB_DATA1 0xFFE01204 +#define ICPLB_DATA2 0xFFE01208 +#define ICPLB_DATA3 0xFFE0120C +#define ICPLB_DATA4 0xFFE01210 +#define ICPLB_DATA5 0xFFE01214 +#define ICPLB_DATA6 0xFFE01218 +#define ICPLB_DATA7 0xFFE0121C +#define ICPLB_DATA8 0xFFE01220 +#define ICPLB_DATA9 0xFFE01224 +#define ICPLB_DATA10 0xFFE01228 +#define ICPLB_DATA11 0xFFE0122C +#define ICPLB_DATA12 0xFFE01230 +#define ICPLB_DATA13 0xFFE01234 +#define ICPLB_DATA14 0xFFE01238 +#define ICPLB_DATA15 0xFFE0123C +#define ITEST_COMMAND 0xFFE01300 +#define ITEST_DATA0 0xFFE01400 +#define ITEST_DATA1 0xFFE01404 +#define SPT0_TX_CONFIG 0xFFC02800 +#define SPT0_RX_CONFIG 0xFFC02802 +#define SPT0_TX 0xFFC02804 +#define SPT0_RX 0xFFC02806 +#define SPT0_TSCLKDIV 0xFFC02808 +#define SPT0_RSCLKDIV 0xFFC0280A +#define SPT0_TFSDIV 0xFFC0280C +#define SPT0_RFSDIV 0xFFC0280E +#define SPT0_STAT 0xFFC02810 +#define SPT0_MTCS0 0xFFC02812 +#define SPT0_MTCS1 0xFFC02814 +#define SPT0_MTCS2 0xFFC02816 +#define SPT0_MTCS3 0xFFC02818 +#define SPT0_MTCS4 0xFFC0281A +#define SPT0_MTCS5 0xFFC0281C +#define SPT0_MTCS6 0xFFC0281E +#define SPT0_MTCS7 0xFFC02820 +#define SPT0_MRCS0 0xFFC02822 +#define SPT0_MRCS1 0xFFC02824 +#define SPT0_MRCS2 0xFFC02826 +#define SPT0_MRCS3 0xFFC02828 +#define SPT0_MRCS4 0xFFC0282A +#define SPT0_MRCS5 0xFFC0282C +#define SPT0_MRCS6 0xFFC0282E +#define SPT0_MRCS7 0xFFC02830 +#define SPT0_MCMC1 0xFFC02832 +#define SPT0_MCMC2 0xFFC02834 +#define SPT0_RX_CURR_PTR 0xFFC02A00 +#define SPT0_RX_CONFIG_DMA 0xFFC02A02 +#define SPT0_RX_START_PG 0xFFC02A04 +#define SPT0_RX_START_ADDR 0xFFC02A06 +#define SPT0_RX_COUNT 0xFFC02A08 +#define SPT0_RX_NEXT_DESCR 0xFFC02A0A +#define SPT0_RX_DESCR_RDY 0xFFC02A0C +#define SPT0_RX_IRQSTAT 0xFFC02A0E +#define SPT0_TX_CURR_PTR 0xFFC02B00 +#define SPT0_TX_CONFIG_DMA 0xFFC02B02 +#define SPT0_TX_START_PG 0xFFC02B04 +#define SPT0_TX_START_ADDR 0xFFC02B06 +#define SPT0_TX_COUNT 0xFFC02B08 +#define SPT0_TX_NEXT_DESCR 0xFFC02B0A +#define SPT0_TX_DESCR_RDY 0xFFC02B0C +#define SPT0_TX_IRQSTAT 0xFFC02B0E +#define SPT1_TX_CONFIG 0xFFC02C00 +#define SPT1_RX_CONFIG 0xFFC02C02 +#define SPT1_TX 0xFFC02C04 +#define SPT1_RX 0xFFC02C06 +#define SPT1_TSCLKDIV 0xFFC02C08 +#define SPT1_RSCLKDIV 0xFFC02C0A +#define SPT1_TFSDIV 0xFFC02C0C +#define SPT1_RFSDIV 0xFFC02C0E +#define SPT1_STAT 0xFFC02C10 +#define SPT1_MTCS0 0xFFC02C12 +#define SPT1_MTCS1 0xFFC02C14 +#define SPT1_MTCS2 0xFFC02C16 +#define SPT1_MTCS3 0xFFC02C18 +#define SPT1_MTCS4 0xFFC02C1A +#define SPT1_MTCS5 0xFFC02C1C +#define SPT1_MTCS6 0xFFC02C1E +#define SPT1_MTCS7 0xFFC02C20 +#define SPT1_MRCS0 0xFFC02C22 +#define SPT1_MRCS1 0xFFC02C24 +#define SPT1_MRCS2 0xFFC02C26 +#define SPT1_MRCS3 0xFFC02C28 +#define SPT1_MRCS4 0xFFC02C2A +#define SPT1_MRCS5 0xFFC02C2C +#define SPT1_MRCS6 0xFFC02C2E +#define SPT1_MRCS7 0xFFC02C30 +#define SPT1_MCMC1 0xFFC02C32 +#define SPT1_MCMC2 0xFFC02C34 +#define SPT1_RX_CURR_PTR 0xFFC02E00 +#define SPT1_RX_CONFIG_DMA 0xFFC02E02 +#define SPT1_RX_START_PG 0xFFC02E04 +#define SPT1_RX_START_ADDR 0xFFC02E06 +#define SPT1_RX_COUNT 0xFFC02E08 +#define SPT1_RX_NEXT_DESCR 0xFFC02E0A +#define SPT1_RX_DESCR_RDY 0xFFC02E0C +#define SPT1_RX_IRQSTAT 0xFFC02E0E +#define SPT1_TX_CURR_PTR 0xFFC02F00 +#define SPT1_TX_CONFIG_DMA 0xFFC02F02 +#define SPT1_TX_START_PG 0xFFC02F04 +#define SPT1_TX_START_ADDR 0xFFC02F06 +#define SPT1_TX_COUNT 0xFFC02F08 +#define SPT1_TX_NEXT_DESCR 0xFFC02F0A +#define SPT1_TX_DESCR_RDY 0xFFC02F0C +#define SPT1_TX_IRQSTAT 0xFFC02F0E +#define SPI0_SPICTL 0xFFC03000 +#define SPI0_SPIFLG 0xFFC03002 +#define SPI0_SPIST 0xFFC03004 +#define SPI0_TDBR 0xFFC03006 +#define SPI0_RDBR 0xFFC03008 +#define SPI0_SPIBAUD 0xFFC0300A +#define SPI0_DMACURR 0xFFC03200 +#define SPI0_DMACONF 0xFFC03202 +#define SPI0_DMASPAGE 0xFFC03204 +#define SPI0_DMASADD 0xFFC03206 +#define SPI0_DMACNT 0xFFC03208 +#define SPI0_DMANEXT 0xFFC0320A +#define SPI0_DMADRDY 0xFFC0320C +#define SPI0_DMAIRQ 0xFFC0320E +#define SPI1_SPICTL 0xFFC03400 +#define SPI1_SPIFLG 0xFFC03402 +#define SPI1_SPIST 0xFFC03404 +#define SPI1_TDBR 0xFFC03406 +#define SPI1_RDBR 0xFFC03408 +#define SPI1_SPIBAUD 0xFFC0340A +#define SPI1_DMACURR 0xFFC03600 +#define SPI1_DMACONF 0xFFC03602 +#define SPI1_DMASPAGE 0xFFC03604 +#define SPI1_DMASADD 0xFFC03606 +#define SPI1_DMACNT 0xFFC03608 +#define SPI1_DMANEXT 0xFFC0360A +#define SPI1_DMADRDY 0xFFC0360C +#define SPI1_DMAIRQ 0xFFC0360E +#define USBD_ID 0xFFC04400 +#define USBD_FRM 0xFFC04402 +#define USBD_FRMAT 0xFFC04404 +#define USBD_EPBUF 0xFFC04406 +#define USBD_STAT 0xFFC04408 +#define USBD_CTRL 0xFFC0440A +#define USBD_GINTR 0xFFC0440C +#define USBD_GMASK 0xFFC0440E +#define USBD_DMACFG 0xFFC04440 +#define USBD_DMABL 0xFFC04442 +#define USBD_DMABH 0xFFC04444 +#define USBD_DMACT 0xFFC04446 +#define USBD_DMAIRQ 0xFFC04448 +#define USBD_INTR0 0xFFC04480 +#define USBD_MASK0 0xFFC04482 +#define USBD_EPCFG0 0xFFC04484 +#define USBD_EPADR0 0xFFC04486 +#define USBD_EPLEN0 0xFFC04488 +#define USBD_INTR1 0xFFC0448A +#define USBD_MASK1 0xFFC0448C +#define USBD_EPCFG1 0xFFC0448E +#define USBD_EPADR1 0xFFC04490 +#define USBD_EPLEN1 0xFFC04492 +#define USBD_INTR2 0xFFC04494 +#define USBD_MASK2 0xFFC04496 +#define USBD_EPCFG2 0xFFC04498 +#define USBD_EPADR2 0xFFC0449A +#define USBD_EPLEN2 0xFFC0449C +#define USBD_INTR3 0xFFC0449E +#define USBD_MASK3 0xFFC044A0 +#define USBD_EPCFG3 0xFFC044A2 +#define USBD_EPADR3 0xFFC044A4 +#define USBD_EPLEN3 0xFFC044A6 +#define USBD_INTR4 0xFFC044A8 +#define USBD_MASK4 0xFFC044AA +#define USBD_EPCFG4 0xFFC044AC +#define USBD_EPADR4 0xFFC044AE +#define USBD_EPLEN4 0xFFC044B0 +#define USBD_INTR5 0xFFC044B2 +#define USBD_MASK5 0xFFC044B4 +#define USBD_EPCFG5 0xFFC044B6 +#define USBD_EPADR5 0xFFC044B8 +#define USBD_EPLEN5 0xFFC044BA +#define USBD_INTR6 0xFFC044BC +#define USBD_MASK6 0xFFC044BE +#define USBD_EPCFG6 0xFFC044C0 +#define USBD_EPADR6 0xFFC044C2 +#define USBD_EPLEN6 0xFFC044C4 +#define USBD_INTR7 0xFFC044C6 +#define USBD_MASK7 0xFFC044C8 +#define USBD_EPCFG7 0xFFC044CA +#define USBD_EPADR7 0xFFC044CC +#define USBD_EPLEN7 0xFFC044CE +#define GPIO_DIR 0xFFC02400 +#define GPIO_FLAG_CLR 0xFFC02404 +#define GPIO_FLAG_SET 0xFFC02406 +#define GPIO_MASKA_CLR 0xFFC02408 +#define GPIO_MASKA_SET 0xFFC0240A +#define GPIO_MASKB_CLR 0xFFC0240C +#define GPIO_MASKB_SET 0xFFC0240E +#define GPIO_POLAR 0xFFC02410 +#define GPIO_EDGE 0xFFC02414 +#define GPIO_BOTH 0xFFC02418 +#define PCI_CTL 0xFFC04000 +#define PCI_STAT 0xFFC04004 +#define PCI_ICTL 0xFFC04008 +#define PCI_MBAP 0xFFC0400C +#defin